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I started studying flip-flops recently and I am stuck at this point:

At some video tutorials, people explain the SR flip-flop like this:

SR1

So they use NAND gates, producing a transition table like this:

|     t     | t+1
|  S  |  R  |  Q
|  0  |  0  |  INVALID
|  0  |  1  |  1
|  1  |  0  |  0
|  1  |  1  |  ?

However, some other people explain the SR flip-flop using NOR gates:

SR2 http://startingelectronics.com/software/VHDL-CPLD-course/tut9-SR-latch/S-R-latch-gates.png

which has a different transition table.

Are both correct? Why do both exist?

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  • \$\begingroup\$ It looks like the picture is wrong S and R should be flipped \$\endgroup\$ – Batman Nov 7 '17 at 1:46
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Both are SR latches.

The SR NOR latch will have the following truth table:

----------
S  R   Q
----------
0  0   no change
0  1   0
1  0   1
1  1   not allowed
----------

SR NAND latch is an inverted version of SR NOR latch. The truth table of which is:

----------
S  R   Q
----------
0  0   not allowed
0  1   1
1  0   0
1  1   no change
----------
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  • 2
    \$\begingroup\$ My professor called it "pushing bubbles" and said that when you push a bubble from input to output or vice versa, the shape changes too. Sounds better than sliding balls, and I still remember it almost 20 years later. \$\endgroup\$ – Matt Jun 14 '18 at 16:02
  • \$\begingroup\$ For the NAND gate, why are inputs S=0 and R=0 not allowed while in NOR they are? \$\endgroup\$ – moonman239 Jun 16 '18 at 22:38
  • \$\begingroup\$ So if you invert S and R before the gate, they behave like each other without the inversion? \$\endgroup\$ – Aaron Franke Sep 17 at 12:50
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There is this this nice small (and incomplete) set of rules about digital circuits, about the little balls to be more precise:

  • little balls can travel around over wires (not always at T sections)
  • little balls can travel across logic gates
  • little balls neutralize each others when they collide

The second needs a little expansion. If you have a little ball on the output of an AND gate, thus making it a NAND gate, you can take the ball, double it, put the new balls in the input and turn the AND in an OR. Things are similar if you start with an OR gate (that with its little ball is a NOR gate). Someone call this rule De Morgan's Laws if you ever have to explain this to a teacher.

Back to your circuit: take the two little balls, cross the NAND gates (splitting the balls). Now you've got two OR gates and four balls. Remembrer that a ball represents a NOT gate:

schematic

simulate this circuit – Schematic created using CircuitLab

Now as you see R and S are negated as soon as they enter the circuit. We can agree and "simplify" NOT3 with R and call that input nR, and similarly with S and NOT2.

Now let's push NOT4 till the T crossing: what happens there? Well you can negate the AND output, and to keep the downstream value of nQ you should put a not there also.

A diagram is worth a thousand words:

schematic

simulate this circuit

Now you can simplify Q and NOT1 and label that output nQ, and simplify nQ and NOT2 and label that output Q. Does the circuit look more familiar now? Your second circuit is just like the same, only what you call set and reset changes.

The real question is: why did I bother with the whole "small balls" story? You could have just written down the truth table and "easily" see what was going on. Well I think that sliding little balls around helps quite a lot in solving simple problems and even a little more complicated ones. Plus it's fun.

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It is possible to construct a simple SR flip flop using NOR or NAND gates. There isn't much difference in the output. The only minor difference occurs because of the properties of a NOR or a NAND gate.

Consider a SR flip flop using NAND gates:-

SR FLIP FLOP USING NAND GATES

The truth table can be given as:-

Truth table for SR FLIP FlOP using NAND

Now, consider SR flip flop using NOR gates:-

SR FLIP FLOP USING NOR GATE

The truth table can be given as:-NOR FLIP FLOP TRUTH TABLE

The circuit will work in a similar way to the NAND gate circuit above, except that the inputs are active HIGH and the invalid condition exists when both its inputs are at logic level “1”. It just depends on the one you prefer to use otherwise both have the same working.

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    \$\begingroup\$ I think your SET and RESET NAND Truth Table is wrong. \$\endgroup\$ – user103497 Mar 14 '16 at 3:47
  • \$\begingroup\$ Your truth tables are swapped. NAND FF: both inputs LO results in both outputs going HI - this is invalid state. Same with NOR FF: both inputs HI results in both outputs going LO - also invalid state. \$\endgroup\$ – Dwayne Reid Nov 7 '17 at 2:09
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NOR gates are used to build active high SR latches and NAND gates to build active low SR latches

YouTube videos about latches

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