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I want to make a Schmitt trigger for a signal, X, who's thresholds are set by two voltages, A and B.

I think I'm having a brain fart. I don't think it's possible to do this with just a single comparator and some resistors, but It would be interesting to know what simplified options there are to do this.

My inelegant half-solution is below:

schematic

simulate this circuit – Schematic created using CircuitLab

Perhaps assume that A is always greater than B, but otherwise they may be any value.

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  • \$\begingroup\$ You mean comparator with hysteresis? \$\endgroup\$ – Golaž Apr 6 '15 at 10:29
  • \$\begingroup\$ Not sure if this page helps. You can fill in values for the resistors and it will show you the thresholds. But perhaps that's not really what you are asking: hyperphysics.phy-astr.gsu.edu/HBASE/electronic/schmitt.html. \$\endgroup\$ – carveone Apr 6 '15 at 10:30
  • \$\begingroup\$ Golaž - I suppose so, but where the points of hysteresis can be determined by two input voltages. Carveone - that would make the points fixed by the resistors - as you say it's not what I wanted :) \$\endgroup\$ – CL22 Apr 6 '15 at 10:34
  • \$\begingroup\$ Hmmm. Having a think about it results in your cct above each time. There is another way but I'm struggling to dig it out of my brain... I believe a 555 timer has two comparators and the requisite logic. \$\endgroup\$ – carveone Apr 6 '15 at 10:43
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    \$\begingroup\$ Ah no wait - the 555 has fixed 1/3 and 2/3 ratios. But the 555 internal circuit in schmitt form is your circuit above (seekic.com/uploadfile/ic-circuit/20114192138589.jpg). Looks like you've reinvented the 555 :-) \$\endgroup\$ – carveone Apr 6 '15 at 10:48
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Something along these lines MAY meet your specification.
I'll not develop the cct fully at this point as eg M1 & M2 may be deemed to be excessive to spec.
If so, what is allowed?
eg are diodes OK - a diode switch could be implemented which is 'unblocked' by high or low output.

Here OA1 +ve output sing has to have Vout > Vhi + Vgsth of M1 and the opposite applies with M2.

Vin connection to IC1-+ input makes this look like negative hysteresis but M1/M2 may invert input polarities depending on how Vhi and Vlo are set. I have not fully thought through what the bounds are on the various voltages or even how they are best switched, but something along these lines looks workable.

schematic

simulate this circuit – Schematic created using CircuitLab

Why only one IC?
Being able to use two probably makes life more straightforward.


A diode gated version could look something like this.

Vlimhi and Vlimlo are either fed to point C via diodes D1 or D4 respectively or blocked by input from Vout via diodes D2 and D3.
R3 is a high value resistor shown as fed from Vdd/2 - but call this Vref instead. This resistor is intended to provide diode conduction of D1 and D4 when they are not blocked by Vout. Vref should lie about midway between the high and low limits and could be provided by a divider between them so it can move as they do. D1 & D4 should be Schottky diodes to minimise difference between the input voltages and opamp input. D1 & D2 maybe be silicon or Schottky.

Odds are that the circuit would need a little playing with to optimise it but it should work well enough for many purposes. I my have made some major error in polarity somewhere but hopefully not. Regardless, the principle should be clear enough.

In the circuit the waveforms at A B C D are all the same in polarity and shape but assume different levels as shown by the captions.


schematic

simulate this circuit


Resistor values are nominal.
R1 R2 stop the IC output fighting directly with the control voltages and R3 is intended to be >> R1 or R2 so reference voltages are not greatly diminished by resistor divider.

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  • \$\begingroup\$ Great solution, very clever. I asked this question because the answer could have been useful in answering other questions I was answering on this site. Twice in two days, and it occurred to me that there might be an IC (or several) which is/are designed to meet this need. I'm intrigued how a diode switch circuit would look! \$\endgroup\$ – CL22 Apr 6 '15 at 14:33
  • \$\begingroup\$ @Jodes Howzat? :-) - I'd be inclined to use more ICs if possible but the diode version "may even be useful" :-). \$\endgroup\$ – Russell McMahon Apr 6 '15 at 16:26
  • \$\begingroup\$ Well I have no idea what a diode switch is, although I may have seen it used - but it doesn't really ring bells. Unless your idea of using diode switches was in fact a joke that I missed! Oh and as for the chip count, I didn't actually say it just had to be one - I just wanted to aim for something neat and simple \$\endgroup\$ – CL22 Apr 6 '15 at 20:15
  • \$\begingroup\$ @Jodes - I think you missed the diagram & notes I'd added to my answer which show a "diode switch". It uses 4 diodes and 3 resistors. Two diodes serve as the "switches" which isolate the two limit voltages from the comparator when "it is not their time to act". The other 2 diodes act as switch control voltage paths, which apply blocking voltage from the comparator output for one polarity and remove it for the other polarity. Diode polarities of switch and blocking diodes are reversed for each input voltage so that one channel works when comparator output is high and the other when it is low. \$\endgroup\$ – Russell McMahon Apr 7 '15 at 2:34
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I've had to design this circuit in the past and what I opted for was two comparators and a D type flip flop. The upper threshold comparator clocked logical 1 into the flip flop and the lower threshold comparator reset the flip flop. It worked of course but I'm intrigued to see if there is a simpler (or more effective) solution.

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  • \$\begingroup\$ Do you mean really mean a D-type flip-flop or an RS latch? A D-type flip flop would require clock and D inputs with characteristics that are always well-defined. If a rising input crosses the upper threshold for a very brief moment and then goes down and back up, it would be hard to avoid having a D flip flop get "confused" and stay that way. An RS latch might get confused when the input briefly went back down, but would the situation would resolve itself when it went back up. \$\endgroup\$ – supercat Apr 6 '15 at 17:47
  • \$\begingroup\$ @supercat I built it with a d type flip flop because we were using one somewhere else on the board. D input was always was set to 1 and the top comparator clocked it in. The lower comparator reset the flip flop. \$\endgroup\$ – Andy aka Apr 6 '15 at 20:44
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Try using a microcontroller like the PIC12F675.

Not sure if you are this inclined or if your requirements allow it but it's something I did in the past for a simple sensor.

Use three of the ADC inputs, one for your signal and two for the thresholds and do your comparison and output activation in software.

Issues may include:

  1. Execution speed may be an issue though depending on your signal frequency.
  2. Voltage level of your signal and its compatibility with the microcontroller input pins.
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If one inverts the polarity of one of the comparators, one may use pair of NAND or NOR gates to build an RS latch; the outputs may then be treated as inverting and non-inverting Schmitt trigger outputs. On the other hand, like all latching circuits, there will be a danger that a signal which crosses the switching threshold of the upper comparator but never stays above it very long may generate runt pulses or another anomalies. If one would wish to condition a signal for use by a counter, a safer approach may be to generate a two-phase non-overlapping clock and then use latches rather than flip flops.

schematic

simulate this circuit – Schematic created using CircuitLab

The SO schematic editor is a little inconvenient, but the circuit below simulates a four-bit counter which will work cleanly even though the input is very noisy, provided that whenever the input brushes against the 4-volt threshold it must go solidly above 4 volts before the next time it brushes against the 1-volt threshold, and whenever it brushes against the 1-volt threshold it must go solidly below 1V before it brushes against the 4V threshold. Note that the phi1 and phi2 clocks generated by the comparators are themselves noisy, but such noise wouldn't matter even if it caused the latches to go momentarily metastable (the latches in this simulator don't do so even under extreme conditions, but real latches might) since any noise event that caused a latch to go metastable would be followed by a valid latching event.

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