In my CycloneV design, I have a 64 bit GPIO port but I only want to connect 40 pins in my design.
If I left it unconnected, Quartus will try to place it and will generate an error because of there not being enough I/Os.
Is there a way to tell pin planner (QuartusII 14.0) to not connect the 24 others pins? Or is it mandatory to modify my VHDL code?
 As asked, here my entity declaration:
Entity gpiochecker is port( [...] gpio0_export : inout std_logic_vector(63 downto 0) := (others => 'X'); gpio1_export : inout std_logic_vector(63 downto 0) := (others => 'X') ); end entity;
I found a solution for input or output pin : using virtual pin :
set_instance_assignment -to signal_name -name VIRTUAL_PIN ON
But that doesn't work in my case because my IO pins are bidirectionnal.