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In my CycloneV design, I have a 64 bit GPIO port but I only want to connect 40 pins in my design.

If I left it unconnected, Quartus will try to place it and will generate an error because of there not being enough I/Os.

Is there a way to tell pin planner (QuartusII 14.0) to not connect the 24 others pins? Or is it mandatory to modify my VHDL code?

[edit] As asked, here my entity declaration:

Entity gpiochecker is
  port(
        [...]
        gpio0_export : inout std_logic_vector(63 downto 0) := (others => 'X'); 
        gpio1_export : inout std_logic_vector(63 downto 0) := (others => 'X')  
 );
end entity;

[edit]

I found a solution for input or output pin : using virtual pin :

set_instance_assignment -to signal_name -name VIRTUAL_PIN ON

But that doesn't work in my case because my IO pins are bidirectionnal.

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  • \$\begingroup\$ Can you show us your top-level entity's ports in VHDL? \$\endgroup\$ – Paebbels Apr 7 '15 at 19:57
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If you don't want to modify your VHDL code, you could create a new top-level entity and then instantiate your existing one inside it. Then you'll have total freedom about whether to connect each pin or not, including input or output pins.

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  • \$\begingroup\$ Yes, I did that. But it's not I wanted to do. Anyways, as I can see it's the only solution :( \$\endgroup\$ – FabienM Apr 8 '15 at 15:09

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