Is there any tool in linux that converts vhdl/verilog code to an equivalent schematic block.
I know the available tools * Synplicity * Synopsys Design Compiler * Altera Quartus II * Xilinx ISE
But these are not free.
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Have a look at tools at http://opencircuitdesign.com/ everything there is open source and free (mostly). I think XCircuit is the software you are looking for http://opencircuitdesign.com/xcircuit/index.html. I myself only check functionality (through simulation) and verify synthesis results so I've never tried XCircuit myself.
If you want to follow complete EDA flow (compile to PnR - maybe even beyond) read http://opencircuitdesign.com/verilog/index.html, in that post all required stuff is mentioned.
If you can't find libraries then look for OSU libraries they are free and can support upto 18micron (I tried 25 micron so not sure about 18).
Apart from these iverilog is really neat compiler. And Emacs code browser is a good editor.
Hope it answers your question.