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# of gates in a 32 bit ripple carry adder?

I know the answer to this question is (4X32=128). But could someone please explain to me why this is the case? I don't understand how they got the 4?

FYI: the full adder implementation is the one without the use of XOR gate in the C-OUT.

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  • \$\begingroup\$ Show us an adder for one bit. How many gates does it have? \$\endgroup\$
    – WhatRoughBeast
    Apr 8, 2015 at 4:35
  • \$\begingroup\$ This is picture of it--- physics.udel.edu/~watson/phys345/protected/exercises/answers/… \$\endgroup\$
    – QWE
    Apr 8, 2015 at 4:44
  • \$\begingroup\$ So how many gates does it have? And how do you know the answer is 4 x 32? \$\endgroup\$
    – WhatRoughBeast
    Apr 8, 2015 at 4:49
  • \$\begingroup\$ Its in my notes: It says a size(# gates) of a 32 bit ripple carry adder is 4 X 32 = 128 and the speed is 32 X 2 X 15ns = 960 ns \$\endgroup\$
    – QWE
    Apr 8, 2015 at 4:51
  • \$\begingroup\$ I believe you flubbed your notes. The 4 gates refers to the logic needed to generate the ripple carry. Since the carry logic is 2 levels per bit, total propagation delay is 32 x 2 x Td. Presumably 15 nsec per gate was provided simply as an example - it bears no relation what you can get in an IC for producing an integrated adder. \$\endgroup\$
    – WhatRoughBeast
    Apr 8, 2015 at 5:00

1 Answer 1

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Here is a 4-bit ripple carry adder (taken from here):

enter image description here

The number of gates for each bit in each full adder is 5. The number of gates just for the carry logic is 3. So the total number of gates for 32 bits would be 5 * 32 = 160. There are also plenty of circuits on the web that use 6 gates instead of 5, e.g. this one, which would be 6 * 32 = 192 gates, and the number of gates just for the carry logic is 4.

The difference between the two circuits, is that the first one (above) uses the output of the first XOR as one of the inputs to the OR gate for the carry. In the second circuit, the carry input to the OR gate is derived directly off of the A and B lines.

What this means is the the first circuit will be two gates delays slower than the second because of the XOR. For the first circuit,, the gate delays to generate a final result will be 2 * N + 2, where N is the number of bits. (2 * N because of the AND and OR gates.) For the second circuit, just 2 * N.

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