How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles needed to go into the interrupt routine differs depending on the instruction being executed at the moment.

• How can I ensure the time from rising edge interrupt until start of the interrupt routine is always the same number of clock cycles?

Except for the interrupt routine there's no code running at the moment, so maybe there's a way to loop with a single instruction in the main code?

• Personally, I'd do all I can to avoid the strategy entirely. I'd clock the data into a shift register, and then shift it out at leisure. – Scott Seidman Apr 9 '15 at 15:58

One option would be to have two triggers, the first causes the code to jump into a loop waiting for the signal to go low and then back high. As soon as the signal has gone back high, then start clocking the data.

Something like:

while(PINREG & (1<<PORTBIT)); //wait for low
while(!(PINREG & (1<<PORTBIT))); //wait for next high