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I am trying to compile a design in modelsim (which I am new to) and I keep getting the following error for one of the files...

(vcom-1491) Empty source files.

I have looked everywhere for a solution and can't find an answer. As far a can see the file is not being compiled into the work directory but I have no idea why.

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I get this error when I try to compile (guess what?) an empty file. In other words, a file with no VHDL statements or declarations in it. Comments do not count as either, so if your file has only comments it is considered empty.

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  • \$\begingroup\$ The file is definitely not empty but I got it to work by renaming the file and copying the contents into a new file with the same name as the old one. \$\endgroup\$ – Marmstrong Apr 13 '15 at 14:25
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After trying numerous avenues I eventually got the file to compile by renaming the file and copying the code into the a new file with the same name as the old one. It mustn't have registered properly or something but this work around worked.

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  • \$\begingroup\$ Ya this happens with modelsim, i have been through this \$\endgroup\$ – Abhishek Tyagi Apr 13 '15 at 14:35
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First save the file when still in the file editor pane.

Seems that if you start with a blank file and didn't save it, the "source file" will be empty. It isn't automatically saved at compile start (opposed to you know, most other compilers..)

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This is a very irritating problem with modelsim. Anyways the solution is simple. Just go to save as and rename the file and save it. It just works..

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One of the reasons that may be in line to what is suggested above and has worked for me is setting the line endings in the editor properly. No need for renaming/resaving.

Check if somehow the line endings in the file that is reported as "empty" are not as expected.

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