The size of a combinatorial circuit is a function of its input. The more input a circuit can use in figuring its output, the larger the circuit must be. Suppose, for example, one needed to design a circuit that would determine whether an input had an even or odd number of rising edges within the last second, if every high and low time was guaranteed to be at least 100ms. One could use a chain of purely-combinatorial buffers with a 91ms propagation time to generate twelve inputs to a circuit that could then count the number of "01" sequences within the bit stream. Such a circuit would be rather large, but not impossible.
If one wanted to make a circuit which could say whether the input had pulsed high an even or odd number of times in the last minute, one could use the same principle, but the result would be rather unwieldy. If one has some clock signal available that may help stabilize timings and prevent the circuit from becoming quite so totally impractical(*), even without feedback (note that combinatorial circuits can use clock signals, but can't generate them). Clock-facilitated optimizations may help prevent a circuit from becoming totally unworkable, but it would still be large. Increasing the time in question to a day, year, decade, or century would likewise grow the machine. If one didn't need the machine to last more than 100 years, one could in theory build a purely-combinatorial machine to report whether the number of pulses in the last 100 years was even or odd, and then use that for up to 100 years, but doing so would be monstrously impractical.
By contrast, using sequential logic, the task could be accomplished using a single D flip flop with an inverted output. Even though in the course of a year the device would be accepting millions of seconds' worth of "input", that would be no problem since a single flip flop will suffice to hold state derived from an unlimited quantity of input.
(*) It's possible to build a D flop without using feedback if one can guarantee that the time between clock pulses will not exceed some limit, though unfortunately this simulator can't handle monolithic MOSFETs.
simulate this circuit – Schematic created using CircuitLab
The "resistors" are actually depletion-mode pull-ups to VDD, and the MOSFETs are monolithic, with their bases tied to VSS rather than to the source. While PHI1 is high, whatever is on IN will be transferred to the gate of M2, and the inverse of it will appear on the M2 drain. When PHI1 is low, whatever was on the gate and drain of M2 will remain there, at least for awhile, because of M2's gate capacitance. When PHI2 is high, whatever is on the drain of M2 will be transferred to the gate of M4, and the inverse of it will appear on the M4 drain. When PHI2 is low, whatever was on the gate and drain of M4 will remain there for awhile because of M4's gate capacitance. Provided that PHI1 and PHI2 do not overlap and are fast enough to reload gate the capacitors before leakage disturbs their values, this circuit may be used reliably as a D flop. Indeed, circuits of this type were very common in 1970s LSI logic.
Further, even if one views this style of circuit as "cheating", it's possible to use clocking to stabilize propagation delays of purely sequential logic by having a clock select between logic paths with shorter or longer propagation times.
simulate this circuit
Unlike the MOSFET circuit, the one above will simulate. Each buffer has a 700ns propagation time, and each mux outputs will change on the rising edge of the clock and no other time provided that rising edges of the clock occur between 700ns and 1400ns after an input change, and the falling edges do not occur until at least 1400ns after an input change. The above circuit initially meets the timing constraints, but because the clock and data are not exact multiples drifts to violate it, showing the consequent behavior.