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My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". Although I have initialized the memory.

Search module>>>

module Search ( 
    clk, 
    rst, 
    SearchData, 
    FindAddress, 
         StopSearch 
); 
input           clk; 
input           rst; 
input[7:0]      SearchData; 
output reg [1:0]   FindAddress; 
output reg StopSearch; 
integer i,x; 

wire read_rq; 
reg [1:0] nxt_address; 
reg [2:0] ii; 
initial 
begin nxt_address=0;i=0; ii=0; end 

wire[7:0] read_data_inx; 

D0_RAM1 D0( 
    .clk(clk), 
    .rst(rst), 
    .read_rq(read_rq), 
    .write_rq(0), 
    .rw_address(nxt_address), 
    .write_data(0), 
    .read_data(read_data_inx) 
); 
always @(posedge clk ) 
begin 
        for ( x =0 ;x <4;x=x+1) begin 
                if (read_data_inx == SearchData)  begin //master i has priority 
                        FindAddress <= nxt_address; 
                        StopSearch <=1; 
      end 

                nxt_address <= nxt_address+1; 
        end 

end 

the RAM module:

module D0_RAM1( 
    clk, 
    rst, 
    read_rq, 
    write_rq, 
    rw_address, 
    write_data, 
    read_data 
); 
input           clk; 
input           rst; 
input           read_rq; 
input           write_rq; 
input[1:0]      rw_address; //2 bit 
input[7:0]      write_data; 
output[7:0]     read_data; 

reg[7:0]     read_data; 
reg[3:0] count_; 
integer out, i; 

// Declare memory 2^2 x8 bits 
// 2^2 = 4 
reg [7:0] memory_ram_d [3:0]; 
reg [7:0] memory_ram_q [3:0]; 
initial 
begin 
count_=0; 
        for (i=0;i<4; i=i+1) begin 
        memory_ram_q[i] <= i; 
                  memory_ram_d[i] <=i; 
                  count_=count_+1; 
                  end 
end 

---> Any ideas?

Thanks.

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  • \$\begingroup\$ What is the purpose of the for loop in the Search module? It looks like the calculation is exactly the same for every value of x. \$\endgroup\$ – The Photon Apr 10 '15 at 20:15
  • 1
    \$\begingroup\$ I think your fundamental issue is that you're trying to use your programming experience for Verilog logic design. Verilog is not a programming language, it's a hardware description language. You need to un-learn your programming habits to be able to master Verilog. \$\endgroup\$ – The Photon Apr 10 '15 at 20:22
  • \$\begingroup\$ purpose of the for loop is to check all memory locations \$\endgroup\$ – H.H Apr 10 '15 at 20:24
  • \$\begingroup\$ You probably want to check one memory location on each clock cycle. Not try to check them all in a single clock period. \$\endgroup\$ – The Photon Apr 10 '15 at 20:32
  • \$\begingroup\$ Remember that for loops in Verilog unroll into hardware circuits that operates in parallel. So you are generating 4 separate circuits that all try to access the RAM at the same time. \$\endgroup\$ – The Photon Apr 10 '15 at 20:39
1
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A physical memory has a fixed number of read (and write) ports. If you want to search for a value inside the RAM, you would need to read every entry. So either you have enough ports to read them all in parallel, or you need to iterate using the read ports you have over multiple cycles.

Really, you need to google CAM (content-addressable memory), that's what you are trying to build, and they are not built from standard memory blocks.

Among other issues in your code: your memory doesn't seem to actually respond to read requests (nothing is driving read_data), so no wonder you get don't care results.

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