Say we have a function, simple as
f(x) = x. Say we have a clock that ticks every 20 nanoseconds, and say we change
x as we wish.
Say there is a clock tick to come, at
t = 20ns exactly (whatever that means). Say
x had been 0 from the
t = 0ns since, and we somehow change the
x into 1 at again exactly
t = 20ns.
Now describe this scenario in Verilog. The question is, what would
f be at
t = 21ns?
Here are the Verilog codes I had written, along with the screenshot from Xilinx ISim simulation window.
module circuit(f, x, clk, rst); output f; input x, clk, rst; wire d, q; d_flip_flop flipper (q, d, clk, rst); assign f = q; assign d = x; endmodule
module d_flip_flop(q, d, clk, rst); output reg q; input d, clk, rst; always @(posedge clk, posedge rst) begin if (rst) q <= 1'b0; else q <= d; end endmodule
And I test these with this
module tester; reg x, clk, rst; wire f; circuit uut (f, x, clk, rst); initial clk <= 0; always #10 clk <= ~clk; initial begin x <= 0; rst <= 0; rst <= #2 1; rst <= #4 0; #10 x <= 1; end endmodule
And here's the waveform I get:
Is this a defined behaviour of Verilog to perform so? If yes, how does it decide upon what should come first in such circumstances?
I have been told by the assistants of the course that what I should really be seeing is actually the opposite, for sure, and I must be doing something wrong if I am seeing otherwise. I would like to know what I am doing wrong, I need help, and they don't provide me this particular help. Could anybody here maybe help?