In my search on building a simple voltage controlled gate delay i stumped upon this chip.
After reading the datasheet i'm still very uncertain if this is the ic i need.
From what i understand: it is programmed using a simple voltage divider and this determines its POL and DIVCODE state.
I need a VC delay that alternates between a rather small ∽1μs and large ∽ 4 sec delay.
But after looking at page 11 and the Table at page 12 of the datasheet it looks like the DIVCODE states has a fixt (still variable) time delay (Recommended tDELAY).
Or am I wrong and could this chip actually vary from its voltage controlled input from 1μs to 33.6 seconds like the fist lines of the datasheet suggest?
Thank you for reading.
Added from OP input with light editing.
These were added as an answer - which may be a good choice**. We can leave them here or as an answer as desired.
I’m very inexperienced and have some difficulty dealing with the equations from the datasheet but understand almost all what has been described so far.
I can’t program AVR or PIC and or make complicated circuits. So this project is for me to learn a bit more.
The application is for a modular synth module, where the gate signals come in externally and the voltage controlled signals come in externally thus from other modules. So the gate signals ratio is all in rather musical tempo’s but the more experimental delay time the better. This to create swing/time offset between a steady flow of gate signals, where I could control the delay time using a simple VC signal from gate to gate in all different tempo’s.
I was first looking at Bucket-brigade devices and had already settled with a limited delay time. The MN3207 does 2.56ms ∽ 51.2ms for instance which is nowhere close to 1μs and could create some timing problems. These require an external clock, which is a disadvantage compared to the LTC6994-2.
The maximum required rates of incoming gate signals is about 20ms per gate. So rise time’s are 40ms apart. This is really fast in musical terms.. (200bpm and 32th notes). Minimum could be 200ms between rise times or so ( 38bpm and 32th notes).
In this module (idee) the voltage controlled delay time response could be set (fine tuned) using a maximum delay time variable resistor and a offset variable resistor that lifts 0v of the VC input. in my op-amp circuit, of the VC input.
The response time and settling time for a new delay time to be programmed (via vc) should be between rise times of the maximum requirements. I don’t need a smooth variation if this means it effects incoming gate lengths, I would prefer the gate time to change in 0v state but since its all experimental it doesn't really matter.
I think I roughly get the inner workings now and how the division work, I’m thankful for that. Although looking at page 17. it says: voltage VCTRL sources/sinks a current through RMOD to vary the ISET current.
What I interpret as that it is possible to vary delay time on the set pin using voltage controlled signals? Although in the range of the programmed division.
At this point if its possible to control SET using VC?, i’m thinking of settling with DIVCODE 4 (4.096ms to 65.54ms) and if its possible to ad a switch to change R2 to program a larger delay time, I would like to know.