This is an introductory level verilog course. I'm trying to generate a 8 bit output from 4 bit multiplied with 4 bit. Here is the code I have so far.
// 4 bit x 4 bit operator module bit4x4Operator( input [3:0]A, //this code works when A and B are switched to 7:0 input [3:0]B, output [7:0]P ); reg [7:0] ROM[0:224]; integer i,k; initial begin for (i = 0; i < 16; i = i+1) for (k = 0; k < 16; k = k + 1) begin ROM [(i * k)] = (i * k); end end assign P = ROM[(A * B)]; endmodule
So, the assignment has to be done implementing the ROM, and this code runs and outputs correctly if the input bits are changed to 7:0, but I'm not sure why that works, and why it can't be the way it is now.