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So I was looking at an Actel A3P250 FPGA for a future project. It has a core voltage of 1.5V and can use 3.3V for the IOs.

So I'm thinking, how do I provide the 1.5V core voltage. My board has 3.3V, 5V and 8-12V variable input as well as an a bulk battery input of 6V - 30V. National Semiconductor has a neat Webench tool. I use the FPGA option, select the exact FPGA and press "Go". It tells me for a core voltage my FPGA needs 1.5V @ 2A. That's much higher than I expected (having no prior experience with FPGAs), but then it also says I need TWO separate 1.5V @ 150mA power supplies (buck converters) for the 1.5V IO and 1.5V PLL each about $3...! This bumps the cost up to a not insignificant $12 for just the supply - the FPGA only costs about $20!

I want to run the FPGA at 250 MHz, to match my SRAM clock. But the IO will be at 3.3V which is already available on my board. So all I need to sort out is the PLL supply. What's stopping me using a 1.5V LDO here? Is there some need for a buck converter?

Does anyone have any idea on how I should architect this power design?

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    \$\begingroup\$ I have seen 5-10 A on design I have worked on. \$\endgroup\$ – Brian Carlton Jul 6 '11 at 23:51
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    \$\begingroup\$ I've always run the PLLs off the core voltage. You just stick a Pi filter in series with the connection to the PLLs, and put a big tantalum after it. \$\endgroup\$ – Connor Wolf Jul 7 '11 at 7:42
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It is very hard to estimate FPGA core power consumption when you haven't yet done the design (I've never done the FPGA design at the point I'm trying to spec the power supplies).

I don't know anything about recent Actel tools and parts, but X and A FPGA tools have power consumption estimation tools which you can play with.

Historically there have been horrible issues with some FPGA families needing huge currents at initialisation, so I tend to be very conservative with supplies for them, just in case. If your design is really cost-sensitive, you should probably build a dev/prototype with a beefy power supply and suitable link where you can measure the actual current, then go for something smaller later.

Your post confuses me somewhat about which supplies you need to provide - there are usually at least three - I/O (sometimes several different bank voltages), core (low voltage, potentially lots of current) and PLL (usually core voltage, low current, should be quiet).

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You might be able to get away with much less current for the core 1.5V supply, and be able to use an LDO. It depends on your application. I'd use an LDO for the PLL supplies, as well.

The Nat Semi tool is probably using worst-case figures for the FPGA.

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  • \$\begingroup\$ There aren't worst-case figures. Since it is so design-dependent the worst-case current is typically more than the package can handle without exotic cooling. \$\endgroup\$ – Brian Carlton Jul 6 '11 at 23:52
  • \$\begingroup\$ My experience is that it's the core supply that consumes the most current. IO and PLL are relatively low consumers in comparison, at least on larger devices. \$\endgroup\$ – akohlsmith Jul 7 '11 at 1:37

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