I was looking for FPGA with PCIe Hard IPs. And I found some FPGAs with more than one Hard IPs. what is the advantage of having more than one Hard IPs in a single FPGA?
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asked Apr 13, 2015 at 3:51
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\$\begingroup\$ Does one hard IP map to one "lane"? In which case you might want more for faster transfer. Or being a PCIe master. \$\endgroup\$– pjc50Commented Apr 13, 2015 at 8:47
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\$\begingroup\$ @pjc50 not getting details about that. Stratix IV GX FPGA has 2 hard IP blocks and it supports 8 lanes. \$\endgroup\$– tollin joseCommented Apr 13, 2015 at 14:24
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1\$\begingroup\$ @pjc50 One lane (one TX/RX pair) is handled by one Transceicer (analog frontend, serial/parallel conversion, channel codind, cross-clock fifo, lane skew minimation). This is one HardIP per lane. All interface bits are aggregated in a PIPE interface that is feed into the PCIe HardIP. This IP implements high level PCIe layers: link and parts of transaction layer. So one additional HardIP per PCIe endpoint is needed. Some IPCores can be configured as a RootComplex - thats not a master because PCI is a multi-master bus. \$\endgroup\$– PaebbelsCommented Apr 13, 2015 at 19:46
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1 Answer
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You need several HardIPs for:
- PCIe bridges
- PCIe Switches
- custom designs that use PCIe as a board-to-board communication
- ...
Common cores support up to 8 lanes and Gen2. More lanes are possible but need a Soft-IPCore. Also Gen3 is mostly provided as a Soft-IPCore.
