I am designing a rather large PCB with straight parallel traces 20cm long carrying CMOS logic at around 100kHz. On top of that I have 8 MOSFETs supplying 5A switching on/off at around 400Hz which a large copper pour as a heatsink located close to logic traces. I am concerned about issues I may have with noise, and given the size of my PCB (250x250mm) it isn't the cheapest thing and I want to get it right first time if I can.

Rather than addressing my specific issues, I was wondering if anyone knew any good articles/books/resources for reducing noise on PCBs? I would like to read up on it and learn more myself.

I found this, which was pretty good: http://focus.ti.com/lit/an/szza009/szza009.pdf

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    \$\begingroup\$ One thing you'll learn once you read those resources is that you don't need to worry about the frequency of your logic, you need to worry about the rise time, which will produce noise at frequencies and harmonics much higher than that. 400 Hz is nothing. Limit the rise time (add a cap and series resistor to the gate trace) of your MOSFETs, and proceed with the design: You're optimizing too early! \$\endgroup\$ Jul 7, 2011 at 17:03
  • \$\begingroup\$ yes its good practice to at least make footprints for a lot of tweaking passive components at key circuit elements like the fet gates. that way you can trim and test without a respin. \$\endgroup\$ Jul 7, 2011 at 23:11

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The best resource that I've found is the book High Speed Digital Design: A Handbook Of Black Magic. While it may not seem to directly address your issues, it does, and many of the concepts do apply-- and it's a good general purpose book for all things related to signal integrity and EMI.

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    \$\begingroup\$ This book is an absolute must-have for any PCB designer or high-speed circuit designer in general. It is ageing, but EM-fields behave the same today as in 1995.. \$\endgroup\$ Jul 7, 2011 at 23:07

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