8
\$\begingroup\$

I've spent the weekend absorbing video lectures from Eric Bogatin and reading his book "Signal and Power Integrity - Simplified"

He states that the the return path for the PCB may be any DC plane which could be a VCC rail underneath the signal path.

Consider the following simple circuit

schematic

simulate this circuit – Schematic created using CircuitLab

If U1 and U2 are placed on the top layer and TX and RX are routed only the top layer, then the return path for the signal (TX to RX) would be Vcc. I'm ok with that.

My question is, when the return current reaches just under the TX pin, where does the current go ? At this point does it find its way to Gnd or does it go back into the TX and through the die, back to ground ?

** Added Text from book **

enter image description here

\$\endgroup\$
10
\$\begingroup\$

When TX switches low-to-high, the current flows like this:

Power supply Vcc -> PCB Vcc plane -> U1.Vcc pin -> U1.TX pin -> U2.RX pin -> U2.Gnd pin -> "return path" -> PCB Gnd plane -> Power supply Gnd

It's great that you understand that what we call the "return path" will be the nearest plane (in this case the Vcc plane). This makes sense as the fields can't read, so they will form between the metal parts in your PCB no matter what you name them.

In the static DC case, the "return path" will actually be the Gnd plane as that will have the lowest impedance. At higher frequencies, the fields will form to the Vcc plane and the current density will be high in the Vcc plane right under the trace.

So how does the current get from the Vcc plane and back to the Gnd plane for the higher frequencies?

Well, remember that the impedance between those two planes is fairly low at these higher frequencies. Actually we want to make the impedance between Vcc and Gnd low across the entire relevant frequency range as well (use something like PDNTOOL.COM to design that), so that is no big surprise (hopefully).

PDN design is well covered in Eric Bogatins book as well.

Let me know if this helped you?

\$\endgroup\$
  • \$\begingroup\$ If you are in EU, there are SI courses in Stockholm (Lee Ritchey) and Copenhagen (Eric Bogatin) in May + June. If you are in the US, Eric does one course this summer as well. ADMIN: Please erase this comment on June 9th, 2015 :-) \$\endgroup\$ – Rolf Ostergaard Apr 13 '15 at 12:34
  • \$\begingroup\$ Not in either country. Was thinking about PCBWEST but I still tons of Eric Bogatin's videos to go through. There are at least 100h worth of content, so I might skip PCBWEST too. But I think I understand more now. Great link, those plots look really familiar from the textbook as well! \$\endgroup\$ – efox29 Apr 13 '15 at 14:26
  • \$\begingroup\$ Anyways - hope this helped. Or? Let me know? \$\endgroup\$ – Rolf Ostergaard Apr 13 '15 at 14:56
  • \$\begingroup\$ It did. Much appreciated ! \$\endgroup\$ – efox29 Apr 13 '15 at 15:19
  • \$\begingroup\$ +1 for link to PDNTOOL --- That's a great little web-app. \$\endgroup\$ – The Photon Apr 13 '15 at 15:54
7
\$\begingroup\$

Hopefully you have provided some power supply bypassing capacitors between VCC and GND near both chips. These bypass capacitors will allow high-frequency currents to flow between VCC and GND.

Note that this means the bypass capacitors become part of the return path, and you need to evaluate the part selection and placement with this in mind.

Also, the driver and receiver circuits within the chips are determine which rail the current flows from. Even if you are using GND as your reference plane, when a driver pulls high it will be pulling current from the VCC rail and so the VCC rail and the bypass capacitors become part of the return path.

\$\endgroup\$
3
\$\begingroup\$

This is something I wondered about as well when I first started until Dr Johnson explained it to me. As you read the return current for a high speed signal will return following the path of least impedance. In a microstrip for example this will be the reference plane closest to it regardless of the DC voltage it carries. As you say a trace referenced to your VCC plane will have it's return current travel along the VCC plane.

Now all current flows in a loop so when it gets back under the chip in your example it will look for the lowest impedance path between VCC and GND which will be your I/O decoupling caps that you have strategically placed near your chip.

\$\endgroup\$
  • \$\begingroup\$ If the decoupling cap is say on the opposite side of pin, would having a via next to pin be beneficial, since it no longer has to travel to the cap ? \$\endgroup\$ – efox29 Apr 13 '15 at 14:29
  • \$\begingroup\$ Not sure I follow you, to you mean a via on the trace right at the pin? In that case the return current still has to find it's way from VCC to GND, and the likely lowest impedance path is still that decoupling capacitor (or perhaps the impedance between the planes but that's more likely at higher frequencies). \$\endgroup\$ – Some Hardware Guy Apr 13 '15 at 14:47
1
\$\begingroup\$

The return path wouldn't be via Vcc.

Think about it in terms of current loops, the TX drive stage & the RX input stage

Take for example this digital I/O (example I/O stages taken from ISO7221 datasheet)

enter image description here

Consider two states

1. TX is high:

enter image description here

In this instance there is an initial "blat" of charge to facilitate turning on the GATE of the RX buffer. After which there is only leakage current flowing (NOTE: this is overlooking termination resistance)

2. TX is low:

enter image description here

In this instance the TX stage holds the pin LOW facilitating current flowing from the pull-up resistor.

In both instances current flows from the +ve of the batter to the -ve of the battery.

Now consider from a PCB point of view. With a contiguous VCC and GND plane under the two IC's, the current that will flow will follow the traces - great small loop.

Lets say there was a break in the GND plane between the two chips, the route the return current would take would not follow that of the TX trace == bad.

\$\endgroup\$
  • \$\begingroup\$ This was how I used to view things as well. But many of the signal integrity books I have read or reading (such Digital Circuit Boards Mach 1 Ghz - Ralph Morrison) or workshops disagree somewhat with this. They view signals as waves and feilds. I'm uploading a pic of some text. Maybe you could elaborate on its meaning ? \$\endgroup\$ – efox29 Apr 13 '15 at 12:17
  • \$\begingroup\$ That doesn't negate what a gnd is though, just tries to help break the association that voltage are referenced to ground - voltage and signal routing is differential \$\endgroup\$ – JonRB Apr 13 '15 at 12:52
  • 3
    \$\begingroup\$ This shows how low frequency components of the signal flow. But when we talk about signal integrity we're also (or more) worried about high frequency components. For the high frequency components the return path will be (mostly) through the plane closest to the signal track. And bypass capacitors will connect the two power rails near each chip. \$\endgroup\$ – The Photon Apr 13 '15 at 15:36

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.