Using a block diagram for the RS flipflop, add appropriate gates for a D-flipflop

I have been given the problem

"Using a block diagram for the RS flipflop, add appropriate gates for a D-flipflop".

Now, I can create the gate diagram for both RS flipflop and D flipflop (below), but I have never been tasked with creating a block diagram. I am a computer science student in a computer architecture class, so you can understand my confusion. I know SE likes questions that can have direct answers, so I'll stray away from asking "Where can I learn to create block diagrams". Instead I'll ask this:

How do I turn these gate diagrams into block diagrams?  • Do you mean functional block diagram - i.e. a box with the input and output lines marked but no circuit details inside? see en.wikipedia.org/wiki/Functional_block_diagram – JIm Dearden Apr 15 '15 at 19:48
• @JImDearden It's possible. I'm not really sure if that's what my professor means. He's frequently very vague on what he really wants. I will take this and do what I can with it. Thank you. – Jaken Herman Apr 15 '15 at 19:50
• Also see the various block diagrams (shown as rectangles with inputs and outputs) in en.wikipedia.org/wiki/Flip-flop_%28electronics%29 – tcrosley Apr 15 '15 at 21:31

Perhaps this might help. I don't answer 'homework /classwork' questions but I'm happy to give you a nudge in the right direction. I've show the block diagrams for an S-R and a NOT S - R flip flop. All you really need to know about them is their truth table.(i.e. the logical relationship between inputs and outputs)

You can create S-R flip flops that change using either an active HIGH pulse or an active LOW. It depends upon which gates you have used to create them.

Its a good idea to show the difference between them (hence the bars above the S and R to show its active LOW).

The problem with a simple S-R type flip flop is that there is a logic race condition. The outputs don't behave when the inputs change and you get both outputs either high or low (0 - 0 or 1 - 1) instead of one being the complement of the other (0 - 1 or 1 - 0).

Imagine what would happen if the Q output operated an accelerator and NOT Q operated a brake in a machine. You could end up with the brake AND the accelerator operated together - not good.

In the case of the NOR gate circuit you never want to have both inputs high at the same time. In the case of the NAND gate circuit you don't want to have both inputs LOW at the same time.

To avoid this race condition extra logic gates can be connected around a basic flip flop to form a D-type, J-K or T (toggle) flip flop.

I think the question being asked is starting with a block diagram of an S-R flip flop add some gates to convert it to a D-type flip flop. You need to decide what constitutes the S-R flip flop (built around NOR gates or built around NAND gates)

I would suggest that you give TWO answers to cover all eventualities.