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I just study about flip-flop in my class and this is the picture from the slide my teacher used that explain the construction of SR Flip-flop

enter image description here

However, I find something was wrong with this figure. If the input are S=1, R=0, Clk=1 at an instant then the out put of the master Latch is Q=1 and Q' = 0. Take that to the input of the Slave Latch. Q = 1 => S of slave latch = 1 but Q' is inverted that make R of the slave make also equal 1 which is forbidden condition.

I think my teacher make a mistake. The right figure should not have the inverter at the complement of output of master Latch but on the clk to en gate of slave Latch

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    \$\begingroup\$ Agree. An easy mistake to make. Good catch. \$\endgroup\$ – WhatRoughBeast Apr 15 '15 at 21:18
  • \$\begingroup\$ The two FF's should be drawn the same -- if there is no inverter on the R input of the first one, there shouldn't be on the second one. Same for the enable inputs -- they should be shown the same on both FF's (as they are now), and should be kept that way. If you need an inverter, it should be shown as a separate gate. \$\endgroup\$ – tcrosley Apr 15 '15 at 21:26
  • \$\begingroup\$ @tcrosley - I've always seen SR flip flops with an inverter on the second enable input. Are you saying this is incorrect or do you just not like that the inverter is shown as a dot and not a separate component? OP - I agree with Rough, your Prof made an oops \$\endgroup\$ – I. Wolfe Apr 15 '15 at 21:54
  • \$\begingroup\$ @I.Wolfe Just a separate inverter like shown here: en.wikipedia.org/wiki/… without the dot on the second FF, such that both FF's are drawn the same. \$\endgroup\$ – tcrosley Apr 16 '15 at 0:43
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For the positive half of the clock, first SR flip flop is enabled. So you will get output at Y and Y'. And for the negative half, second flip flop is enabled and you will get output at Q and Q'

That means, effectively you get respective output at starting of negative half (neg edge) of the clock signal.

enter image description here

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