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This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered.

I have Verilog code to multiply two matrices and read them out, but my throughput is limited significantly by the number of I/O pins on the Xilinx Virtex 5 board (http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf) we would be using. (I am designing on the Xilinx ISE)

How do I know which of the pins mentioned in the datasheet may be used as digital output pins? I've been through the datasheet several times, but I can't figure out which of the pins may be used for reading my matrices out (I estimated the number to be ~20-30, but not sure).

Thank you!

PS: I'd like to use every output pin I have, since we shan't be implementing on the board, but just calculating theoretical maximum throughput)

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  • \$\begingroup\$ Can you give the exact board name? UG347 is for three boards. \$\endgroup\$ – Paebbels Mar 20 '15 at 8:09
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This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered.

I flag this question to be moved to Electrical Engineering -> that's the right place :)

FPGAs are digital circuits, so normally there are only a few analog pins. For example a XC5VLX50T on a ML505 board is assembled in a FFG1136 package. That means the chip has 1136 pins. 480 of them are for digital I/O.

Resources:

BUT

Reading out matrices from GPIO pins is the solution to your question! You should use a normal communication interface like: PCIe, Ethernet or UART to transfer data to and from FPGA.

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    \$\begingroup\$ Agreed. Also note that while all pins can be used as output, you have some restrictions depending on IOSTANDARD and simultaneous switching output (SSO). It is unlikely all pins could be used as output, besides, how would you get data in then? \$\endgroup\$ – Jonathan Drolet Mar 20 '15 at 12:25
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The biggest FPGA you can get on that board is the XC5VFX70T in the FFG1136 package. That chip has 640 GPIO pins and 16 GTX transceivers. The GTX transceivers are good to 6.5 Gbit/sec, so they can do PCIe gen 2 at 5 Gbit/sec per lane. If you use all 16 transceivers, that's 104 Gbit/sec at 6.5 Gbit/sec/transceiver or 80 Gbit/sec at 5 Gbit/sec/transceiver both ways (each transceiver gives you a TX pair and an RX pair). The raw I/O pins should be able to run up to 1.25 Gbit/sec as LVDS pairs, so that would be around 400 Gbit/sec one way. However, that would be a major ratsnest of connections, it would likely be a better idea to only consider the GTX transceivers. Also, don't forget that the I/O interface logic could take up a significant amount of logic resources, especially if you are trying to bring all of the I/O pins to bear.

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