# Behavior of logic gates when one input is undefined?

I tried to understand to behavior of this circuit when it has no voltage supply at first which means the current state is neither 0 or 1. You can say that there is a 'nothing' input. Then when the switch on digital pulse go to the input but there is a 2-input AND gate but there is only 1 known input because there's no signal at first so I don't know how it would behave this time as the outputs of A, B, and y are neither 0 or 1 so I can't use the truth table or state equation which is a function of the input and present state. There is no present state here to begin with.

If I follow the truth table, then A=0, B=0, x=0 result in A=0, B=1, y=0 in next stage. However, when there is no voltage supply at first. A is not equal 0 because if A equal zero then A'=1 which require voltage supply but there is no voltage supply to make it so • If there is no voltage supply, the logic gates won't work either. Therefore you should not care what any of the logic states are. However, if one input is undefined, the behavior of the logic gate is unpredictable as the input is also unpredictable. – MrPhooky Apr 16 '15 at 8:04

You are correct. That is why an actual real-life circuit would need to be initialized the first time with x=1.

It's sometimes important to recognize two distinct kinds of "AND" gates, and likewise with "OR", "NAND", "NOR", etc.

1. Those where a valid high on all inputs will guarantee a valid high output, and where a valid low signal at any input will imply that the output will be low, whether or not other inputs are at valid logic levels.

2. Those where a valid high on all inputs will guarantee a valid high output, and where a valid low signal at any input accompanied by valid high or low signals on all the others will imply that the output will be low, but if any inputs are at invalid levels the output may arbitrarily appear as a valid high, a valid low, or an invalid signal.

Most gates implemented in discrete logic behave in the former fashion. Gates which are combined into other logic, however, especially in a CPLD or FPGA, may not always do so. Additionally, while flip flops normally power up in a valid high or valid low state, there are cases in which they may power up in, or enter because of setup/hold violations, weird states which may output invalid logic levels.

If your circuit is drawn with the former style of gates, then a clock pulse which arrives when X is a valid low (and has been in such fashion as to satisfy register timing requirements) the next clock pulse will cause both registers to latch a valid low. If either flip flop is outputting a valid high while X is a valid low, Y will be high until the next clock pulse or until X ceases to be low. If both registers hold valid lows when X goes high, succeeding pulses will yield A=0 B=1, A=1 B=1, A=1 B=0; the circuit will then remain in the latter state.

If the circuit is drawn with the latter style of gates, is behavior will likely be much less certain. It would in practice probably stabilize after awhile to A=1 B=0, but that's hardly guaranteed.

It is undefined "within the constraints that each output or input can only be 0 or 1". At some point, the power supply will stabilize, the clock will clock and the magic happens whether you want or don't want it. If clocked, something will happen based on inputs.

It's why we apply reset pulses which are longer than power supply stabilization.

As for the circuit.

$$D_1 = xA + xB$$ $$D_2 = x \bar A$$ $$y = \bar x (A + B)$$

$$\begin{array}{c|ccc|cc} Clk & \text{A} & \text{B} & \text{x} & \text{A} & \text{B}& \text{y}\\ \hline ↑ & 0 & 0 & 0 & 0 & 0 & 0\\ ↑ & 0 & 0 & 1 & 0 & 1 & 0\\ 1/0 & 0 & 1 & 0 & 0 & 0 & 1\\ ↑ & 0 & 1 & 0 & 0 & 0 & 0\\ ↑ & 0 & 1 & 1 & 1 & 1 & 0\\ 1/0 & 1 & 0 & 0 & 0 & 0 & 1\\ ↑ & 1 & 0 & 0 & 0 & 0 & 0\\ ↑ & 1 & 0 & 1 & 1 & 0 & 0\\ 1/0 & 1 & 1 & 0 & 0 & 0 & 1\\ ↑ & 1 & 1 & 0 & 0 & 0 & 0\\ ↑ & 1 & 1 & 1 & 1 & 0 & 0\\ \end{array}$$

Edit..

If x = 0. Both A & B are 0.

When x goes 1, B goes true on first clock. A & B will be true on second clock. Only A will be true after 3rd clock.

y only is true when x goes 0, before CLK occurs (+ propagation delays) latching 0 into A and B. It occurs every time x transitions to 0.

No matter what state A or B start in (random). After a couple of clocks (worst case), the state machine will reset itself to the state of x.

No reset required. x = 0, A & B will be 0. x = 1, after 3 clocks A = 1 and B = 0.

• Why do rows 011, 100, and 110 not have y=1? – supercat Apr 17 '15 at 19:50