In Design of Analog CMOS integrated circuits by Razavi I found the following differential pair design. It uses a MOS as load and it acts as a current source.
My question is how should you bias the current source loads? My initial guess would be that M3 and M4 should be biased so that the current through them is Iss/2, because this is the current that also goes through M1 and M2 when Vin = 0.
Now comes the bit where I become confused. As far as I know differntial pairs are designed so that when the maximum input voltage is supplied one of the transistors (M1 or M2) is fully on and the other one is fully off. This was the case with differential amplifiers that have a restive or diode connected mosfet as load.
However, with current sources as load this will cause a current conflict between the differential pair en the current source loads. For example: The maximum input voltage is applied and therefore M1 is fully on and M2 is fully off. Now M3 should supply Iss since M1 is fully on, but its source and gate are fixed so it is limited to Iss/2. Furthermore, M2 is fully of, but M4 tries to force Iss/2.
So what am I missing? Why does this circuit work?