# Current source as load in a differential amplifier

In Design of Analog CMOS integrated circuits by Razavi I found the following differential pair design. It uses a MOS as load and it acts as a current source. My question is how should you bias the current source loads? My initial guess would be that M3 and M4 should be biased so that the current through them is Iss/2, because this is the current that also goes through M1 and M2 when Vin = 0.

Now comes the bit where I become confused. As far as I know differntial pairs are designed so that when the maximum input voltage is supplied one of the transistors (M1 or M2) is fully on and the other one is fully off. This was the case with differential amplifiers that have a restive or diode connected mosfet as load. However, with current sources as load this will cause a current conflict between the differential pair en the current source loads. For example: The maximum input voltage is applied and therefore M1 is fully on and M2 is fully off. Now M3 should supply Iss since M1 is fully on, but its source and gate are fixed so it is limited to Iss/2. Furthermore, M2 is fully of, but M4 tries to force Iss/2.

So what am I missing? Why does this circuit work?

• +1 because the average question here is about how to turn on a led Apr 16 '15 at 9:22

Your initial guess is right: you size M3 and M4 so that with zero differential input the current through the two branches is the same, i.e. Iss/2.

For small differential inputs this condition is always nearly true, i.e. the current through M1 and M2 drains is nearly Iss/2 if you neglect a very tiny difference. Luckily enough this very tiny difference flows in the output resistance of M3 and M4, that is very high, thus producing an high output voltage swing and (hopefully) your required gain.

When you apply a big signal, such as what you describe in the last part of your question, many things happen. The most important is that your previous models does not work any more: you just can't treat M3 and M4 as ideal current sources because some hypothesis you made are no longer true.

Let's say you apply the maximum input voltage: M1 is fully on and M2 is fully off. Let's also assume that Iss is ideal. All the current must flow through the left branch, and none can flow in the right since M2 is off. M3 will accomodate for the higher current with an higher Vds, that's where the assumption M3 and M4 carry the same current fails: their Vds is now quite different.

Since for M3 you know Vgs and Ids the Vds is known too -> you can calculate the output voltage. What you can't know is M1 Vds, together with its Vgs. What happens here is that the ideal current source provides the necessary drain voltage to keep the circuit standing on its feet, possibly a voltage below ground.

If that is not an ideal current source, but a mosfet, say M5, then the whole story is a battle between M5 and M3: M5 drain voltage (i.e. M1 source voltage) will start to go down, it would really like to go even below ground, but unfortunately you probably need some saturation voltage on that node (~200mV), below that M5 just stops behaving like a current source and its drain current drops, and you finally get zero current on the right branch, and a current that's between Iss/2 and Iss on the left branch.

Question 1) Simply bias them so that their currents are equal. The "current mirror" configuration does exactly that - then you need no knowledge of what Iss actually is.

Question 2) You are correct : there is a conflict between the two requirements (M1 on, M2 off) and equal current in M3,M4. This conflict is what gives the extremely high open-loop gain of the stage.

Consider its actual use : as soon as you start to turn M1 on, it attempts to draw slightly more current but M3 resists that. The result is a large change in Vout. If the device is open loop (a comparator) Vout will get pretty close to the supply voltage and trigger the comparator logic.

However in an amplifier, Vout is connected back to Vin(M2) via a negative feedback network (external components), so restoring the balance between the input transistors.