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I'm not even sure if this should go here on the EE StackExchange or if there's a CAD board, but I'm posting it here just in case. I am working on a 2-sided SMD PCB that has vias and SMD pads. On the pads (which I will be soldering) I need to have a relief connect for the polygon pour of the same net, but I need a direct connection on the Vias of the same net. I currently have all Relief connects:

relief connects

But in the Design Rules I cannot find an option that would set Vias aside from component pads:

design rules

I considered adding all of the vias to a class, but I can't seem to be able to do that either. To make this even more difficult, I have two QFNs with thermal pads that use built-in vias to stitch through the board. These should NOT have a direct connection to the polygon as it will make it much more difficult to solder.

Is there a way to add, say, selected vias to a class? I just need to set a rule for the Polygon Connect to use direct connections over specific vias, and relief connections over the rest of the PCB. Thanks!

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  • \$\begingroup\$ Sometimes the distinction between vias and pads is a bit infuriating. In this case, you can "convert vias to free pads" and then add those pads to a class. \$\endgroup\$
    – The Photon
    Apr 16, 2015 at 16:23
  • \$\begingroup\$ Thanks for the reply, I was about to try this but when brhans' answer came up, it seemed easier to implement so I did that one instead \$\endgroup\$
    – DerStrom8
    Apr 16, 2015 at 16:32
  • \$\begingroup\$ For anyone else reading this, @ThePhoton's suggestion works too, just requires a little more work =) \$\endgroup\$
    – DerStrom8
    Apr 16, 2015 at 16:41
  • \$\begingroup\$ Got back to altium after a couple of years of using Orcad. I have this idea this was buried in the settings somewhere or wasn't this done with queries somehow. But a simple google search saves hours of going over documentation.. \$\endgroup\$
    – Barleyman
    Mar 23, 2018 at 15:30

3 Answers 3

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When you're setting up a new PCB rule, you can type "query text" to match objects to which the rule should apply.
When I do what you're trying to do, I just use "isVia" as the query text and then set the Connect Style to Direct Connect:

enter image description here

I'm not sure how to exclude your QFN's thermal stitching vias though...

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    \$\begingroup\$ Thank you so much! Did not know that query component was even there! Anyway, I ended up doing the following to exclude the vias on the thermal pads: isVia AND NOT (InComponent('U2') OR InComponent('U3')) \$\endgroup\$
    – DerStrom8
    Apr 16, 2015 at 16:32
  • \$\begingroup\$ This is old news, but another option to get special behavior for the stitching vias is to add a rule that picks out those vias (either by InComponent() or HasFootprint(), for example), and just give that rule higher priority than the more general rule for most vias. \$\endgroup\$
    – The Photon
    Nov 5, 2015 at 17:04
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    \$\begingroup\$ Also adding a comment: if you're trying to specifically make only stitching or shielding vias exempt, you can use "IsStitchingVia" for stitching vias and "IsShieldingVia" for shielding vias. \$\endgroup\$
    – Synchrondyne
    Nov 18, 2015 at 20:11
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I don't know your Altium's version, but in 17.0 is easier. Inside the rules menu, in the polygon connect rule, just click Advanced and you can change the rule for the vias or the through hole: enter image description here

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  • \$\begingroup\$ Altium 17 definitely made things easier. At the time I originally posted this question I was using 16 and all I needed was the "isVia" query to sort it out. Thanks! \$\endgroup\$
    – DerStrom8
    Mar 5, 2018 at 16:37
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To enhance thermal dissipation as recommended by Analog devices for the LTM8071, I wanted direct connect vias interlaced between the balls under our BGA. This did actually work and not cause assembly issues on the rev 1 version of our board but I had to drop them down manually and give special instructions to the fab house.

My first attempt to improve this was to make the new part with the balls and interlaced vias. However, I think there is a bug which wouldn't let me ECO that new part in place of my old part because it would ignore my ground connection to my newly updated part with the interlaced vias.

So, all I did was drop down a bunch of vias of an odd size (like 17mil) and then did a custom Polygon Pour rule where any via with ViaSize=17 gets a direct connect. Brute force. You could make a union out of the whole thing I think. But be sure to specify tenting or just soldermask fill to cover those vias or you might have BGA assembly issues.

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