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I was checking ATMEGA16 datasheet , and at pg17 I found that there is the IO registers that happen to have " IO addresses and SRAM addresses " ,

I don't know which we use and why there is two kinds of addressing for IOs ?

I need to know if it's part of the SRAM or not , Please enlight me ^^

Page 17 Data address space

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  • \$\begingroup\$ That's how they can access registers via memory addresses. Memory mapping goodness. \$\endgroup\$ – KyranF Apr 17 '15 at 17:00
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Without accessibility from data space (not "via SRAM") there would be no way to perform indexed/indirect addressing of registers, adding complexity to a large number of algorithms and programming methods. On the other hand, having I/O space allows IN and OUT to be single-word instructions, reducing the size and runtime of simple code.

Register space is independent of SRAM space, and the SRAM is moved up the appropriate number of locations in data space to compensate.

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This is just a processor design choice.

You are probably surprised, because, say, on an Intel x86 processor, a register like EAX doesn't have a memory address; it lives only inside the processor.

It has to be that way on a high performance computer, because accessing memory is costly. Registers are used precisely because they are not memory: they are very high speed storage locations that are in the processor itself.

An advantage of having registers mapped to memory is that the machine state is an object in memory. If you have a snapshot of some memory range, then you have a snapshot of the machine state. And if you have a debugging tool which can access memory, you know the machine state.

So then the second question might be: if a processor has registers which are actually just memory locations, why bother with registers at all if they are just "fake", and denote memory locations? The instruction set can just deal strictly with memory operands and no registers.

Part of the answer to that is that registers can make for a smaller instruction encoding. If you have, say, eight registers, then only three bits are needed in an instruction to designate that register. You then have more bits available for more instructions, or more addressing modes.

Possibly, the "machine with fake registers" can actually have registers on the processor die, which are only synchronized with the ones in memory. That is to say, it is not necessary for a read access to register R0 to actually access the memory $0000; there can still be an internal R0. To keep the internal R0 synchronized, the processor can snoop the bus and when it detects that something (possibly itself) writes to the word at location $0000, it updates the internal R0 with the same data. (Note: not saying that your AVR does this!) Similarly, if a value is loaded into R0, it can immediately go to the internal R0, but the external update of $0000 can perhaps lag behind a little bit; the machine's execution does not have to stall until that update completes. If the next instruction requires the value of R0, it does not necessarily have to wait until a memory cycle finishes updating $0000.

There are instruction sets without registers. Stack machines are an example of instruction sets which achieve good instruction size, without registers. Instead of registers, there is an stack, and most operations work with one or two operands at the top of the stack. The operations do not have to indicate the source or destination at all; the stack is implicitly used.

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It's a code size thing. There are single word instructions that access I/O memory that contain the entire I/O address as an immediate value (encoded within the instruction). A full SRAM address is too long to fit into a single word instruction, so the equivalent instructions that access the SRAM address space require two words. Also, there is no way to do indirect addressing to I/O space directly, so it has to be mapped into SRAM space as well so that all of the assessing modes can be used. Basically, the I/O space is just a 'short cut' for memory locations that are accessed often with constant addresses (i.e. accessing I/O ports) and the I/O space provides a code size and speed benefit (two word instructions take two clock cycles to process). Additionally, the low portion of the SRAM space is 'bit addressable' so instructions that operate on individual bits can access the general purpose processor registers as well as the I/O registers.

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1- limited 2 bytes access

2-dircet and indirect addressing Direct add

Indirect

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  • \$\begingroup\$ The text in your answer doesn't really explain how this works - it just describes what's in the picture. It's not really clear how well this answers the question. Can you be a bit more descriptive/verbose? \$\endgroup\$ – Greg d'Eon Apr 18 '15 at 11:56
  • \$\begingroup\$ you see in I/O registers $00 which needs only 2 cycles one for address and other for the opr. but limited to 2^8 =256,also in direct i can only do j 0x0000 - jump to absolute add 0x0000- while have reg i can do jr $s0,2($i0) - s0 contains the data while i0 contains the address and 2 is offset \$\endgroup\$ – Mohammed Mustafa Kamel Apr 18 '15 at 12:50
  • \$\begingroup\$ You could edit that into your answer. \$\endgroup\$ – Greg d'Eon Apr 18 '15 at 13:10

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