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I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) .

I used INSTANTIATION as below:

RAM1 RAM_NAME (                 
  .clka(clka), // input clka             
  .wea(wea), // input [0 : 0] wea                 
  .addra(addra), // input [6 : 0] addra                  
  .dina(dina), // input [7 : 0] dina               
  .douta(douta) // output [7 : 0] douta             
);

I am able to do synthesis but when i am doing implement design. It is giving error:

ERROR:NgdBuild:604 - logical block
'Leena/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/raml
oop[0].ram.r/s3a_init.ram/spram.ram' with type 'RAMB16BWE' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'RAMB16BWE' is not supported in target
'spartan3e'.

What are the cause of above error and how can i correct it?

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Xilinx's Spartan-3E only support RAMB16, RAMB16WE being a primitive of a later architecture (Spartan-3A, and maybe others).

You most likely generated your IP with the wrong project options. Make sure you generate the IP for a Spartan-3E, not a Spartan-3A or any other architecture.

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  • \$\begingroup\$ In my case, I had 2 problems but neither were the target. I needed a NET definition in my *.ucf file for the missing pin(s). I was also missing a source file that was needed by one of the others I had brought in. \$\endgroup\$ – CrazyPyro Apr 23 '15 at 22:46

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