# is flip flop a synchronous or an asynchronous sequential circuit?

i have read in my text book that : " A flip-flop is the simplest synchronous sequential circuit. "

but it is not convincing at all since we cannot analyze or build a flip flop like a synchronous circuit .

even i asked a question about how to design a flip flop with having it's truth table .

designing a sequential circuit by having it's value table?

and the person who answered (Francesco Conti) claimed that flip flops are asynchronous circuits ?

what type are flip flops ?

EDIT by flip flop i mean an edge triggered D flip flop .

the best definition i could find of synchronous and asynchronous circuits is here: http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part3/sa-op.htm

it states that :

Synchronous sequential circuits change their states and output values at discrete instants of time, which are specified by the rising and falling edge of a free-running clock signal

In asynchronous sequential circuits, the transition from one state to another is initiated by the change in the primary inputs; there is no external synchronization.

After Reading the proper answer i think we can say that :

if you look at a D-flipflop as a whole it's function IS synchronous

BUT since it's the building block of synchronous circuits obviously it's not possible to design it like a synchronous circuit (since then we would use FlipFlops to design FlipFlops) so it's design is like asynchronous circuits and has no algorithm.

to sum it up since the flip flops are the elements that make the transition from asynchronous to synchronous possible ; (in other words they are the building blocks of the synchronous circuits ) then they are some where between synchronous and asynchronous circuits .

their design is asynchronous since they are the first synchronous circuit to be made.(so they must emerge from asynchronous circuits and asynchronous design)

while their function is synchronous .(they change their states and output values at discrete instants of time)

• There is no 100% agreement on what exactly flip-flop is, so you should state to which circuit or logical element you refer with the term 'flip flop'. Apr 18, 2015 at 16:49
• Seems like, if it's got a clock input, it's synchronous. Apr 18, 2015 at 18:19

Internally, a flip-flop (the term includes everything from simple D latches to more complex edge-triggered J-K master-slave flip-flops) is an asynchronous state machine. It is created by combining ordinary logic gates with feedback.

For example, here's one way to construct a master-slave D flip-flop:

simulate this circuit – Schematic created using CircuitLab

Each of the internal sections is a simple set-reset latch with an enable input. Because the two enables are driven with opposite levels of the "CLK" input, the output can only change state on its rising edge.

Note that while this design is conceptually simple to understand, it is NOT typical of how commercial chips (e.g., 7400-series) are constructed internally. If you study SSI/MSI databooks (the older TI books were especially good), you'll see several other ways to construct flip-flops from gates.

Once you have an edge-triggered flip-flop of any sort, you can use it (or multiple copies of it) to create synchronous state machines that only make transitions on clock edges.

• so we can say that if you look at a D-flipflop as a whole it's function IS synchronous BUT since it's the building block of synchronous circuits obviously it's not possible to design it like a synchronous circuit (since then we would use FlipFlops to design FlipFlops) so it's design is like asynchronous circuits and has no algorithm.
– KFkf
May 1, 2015 at 10:27

I think when most people use the term "flip-flop" they are talking about an "edge triggered D-Flip-Flop." Such a flip flop is a synchronous sequential circuit. It's output only changes on clock edges. Here is a state diagram for one:

... and here is it's state transition table:

Input  Current State  Next State  Output (synchronous)
0      0              0           0
0      1              0           1
1      0              1           0
1      1              1           1


That is to say, the the output = current state (always), and the next state = the input (when the clock edge occurs).

• then how come we can't design then like other synchronous sequential circuits ? . i mean we cannot do it like making a state diagram and then a state table and then making the circuit . take a look at my question electronics.stackexchange.com/questions/164227/…
– KFkf
Apr 18, 2015 at 17:06
• @kiyarash that is because the premise of conventional clocked sequential circuit design is that the state holding elements are D-flip-flops. That being said, it's trivial to draw a state diagram for one and write out its state transition table. Apr 18, 2015 at 17:09
• but it is not possible to make a circuit from the table or diagram . that's what i mean !
– KFkf
Apr 18, 2015 at 17:26
• i mean there is no algorithm to design them like other synchronous circuits . i mean can we for example design a D flip flop that is triggered on both clock edges in an algorithmic way ?
– KFkf
Apr 18, 2015 at 17:29
• I think you're missing the point of the OP's question: He wants to know how the flip-flop itself is designed and/or implemented. What is it that makes it edge-triggered? Apr 18, 2015 at 18:09

Edge triggered D flip-flop is an asynchronous circuit. You can see one of the implementation below. I like this one because you can analyze this, simulate it and even build it using standard gates. Not only that, you can see where typical parameters for edge triggered circuits such as setup and hold times come from. It is essentially 3 SR latches interlocked in certain way.

Let's take this through one set of {inputs, outputs}. Then you can analyze it for others.

Let's assume CLK=0, D=0 at power up. Also assume QB=1, Q=0. It is equally likely that it may come up as QB=0, Q=1. You can think of how you will add reset in this circuit.

As CLK=0 and D=0, you get {O1, O2, O3, O4} as {0, 1, 1, 1}. Because O2 and O3 are 1 each, QB and Q remain stable, in this case as 1 and 0.

Now, lets assume D makes transition 0->1. This will change {O1, O2, O3, O4} as {1, 1, 1, 0}. Still no effect on QB, Q.

This transition needs to pass through G4 and G1 in order to propagate all the way to one of the inputs of G2. This will define setup time as (delay(G1) + delay(G4))

Now let CLK makes transition from 0->1. If you analyze all inputs to G1, G2, G3 and G4, you can see that {O1, O2, O3, O4} will change to {1, 0, 1, 0}. This will propagate to QB and Q and make them QB=0, Q=1.

D input need to be held to stable value after CLK transition for delay equal to delay(G2). That is hold time.

You can verify that after this delay, if D changes, there is no effect on output. Also there is no effect on output when CLK makes transition from 1->0.

simulate this circuit – Schematic created using CircuitLab

This comes from one of the older text books, "Logic Circuit Design" by Prof. D. Zissos.

There are synchronous and also asynchronous flip-flops.

But If you are talking about "edge triggered D flip flop" then that implies a synchronous one.

• isn't an "asynchronous flip flop" typically called a "latch"? Apr 18, 2015 at 17:21
• No. Latch is a different thing. But talking about asynchronous D flip-flop doesn't make really any sense - it has no practical use. This is how it looks: i.imgur.com/DUonK7l.png Apr 18, 2015 at 17:34
• I think you're missing the point of the OP's question: He wants to know how the flip-flop itself is designed and/or implemented. What is it that makes it edge-triggered? Apr 18, 2015 at 18:39