# Will cutting power to a CMOS chip effectively remove it from the circuit?

I have some designs that require several 4017 ICs to be switched in and out of the circuit intermittently, for counting circuits that require more than 10 outputs.
The way I am currently designing this is to have a master counter, with outputs connected to Vcc of the slave 4017s, to basically remove the chip from the circuit and activate the next one when the count advances.
Will this approach work, or will the chips suck power from another pin?
Also, is there a counter chip similar to the 4017s but with more than 10 outputs?
Thanks!

• How do you mean? Can you include a circuit diagram? Or picture to explain this a little better. – Dean Jul 9 '11 at 0:02
• working on circuit diagram right now... – Nate Koppenhaver Jul 9 '11 at 0:06
• for some odd reason, it's not letting me add a picture... – Nate Koppenhaver Jul 9 '11 at 0:09
• I have seen cmos parts being powered from their I/O inputs. – old_timer Jul 9 '11 at 2:11

The quick answer is, no. It won't work. Most IC's have ESD protection diodes on the inputs and sometimes the outputs. If the chip is powered down, it will be like having a diode to 0 volts on the signal. Best case, that signal will see a large load on it. Worst case, the signal+diode will actually cause VCC to go up, causing the chip to actually power up.

Here's a schematic that shows some protection diodes. The schematic isn't great, but it does the job. Imagine everything to the right of the dashed line to be inside the chip:

The two diodes from ground and to VDD are there to prevent the input signal from going too much above or below the power rails. Everything to the right of the diodes can safely be ignored, as they are chip specific.

As you can see, if the input goes above VDD (which is 0 volts when powered down) then there is a current path from the pin to VDD.

• That the input voltage will power the device via the clamping diode is proved here (as mentioned in this answer) – Federico Russo Jul 9 '11 at 5:59
• Danger! Will Robinson :-). That proves that powering via the body diodes MAY work. The issue is not whether you can get power to Vdd and Ground this way - as you certainly can - but what else MAY happen when you do this. As per my recent protection diode post, 'strange and unusual' results may occur and there is no certainty that side effects will be consistent or predictable. All that said, powering circuits this way can be 'lots of fun' if you are willing to accept the possible consequences. – Russell McMahon Jul 9 '11 at 21:36
• @Russell McMahon: Because many devices work as though there are simply diodes connected as indicated, it's easy to assume all devices will do so. In fact, there are many different ways devices can behave when pins are driven below Vss or above Vdd. Sometimes the behavior of parasitic transistors will be such that there will be no particular problem if a pin is driven above Vdd with a limited amount of current, but it will be impossible to power a device from a port pin. Actually, in some cases that could be a feature. – supercat Jul 10 '11 at 18:48
• @Russell McMahon: For example, if a device had a PNP transistor on each I/O pin, with the emitter tied to the pin, the base tied to Vdd, and the collector tied to Vss, such a device wouldn't be able to survive as much sustained current as a clamp diode (since its voltage drop would be Vdd+0.7 volts rather than 0.7 volts) but most of the injected current would be sinked to Vss rather than Vdd. I've never seen a device spec'ed that way, though I've done a number of designs where it would have been helpful (since parasitic powering proved problematic). – supercat Jul 10 '11 at 18:53

Check the data sheet. Most devices will specify that some or all of the pins must remain in the range Vss-0.3V to Vdd+0.3V, or something similar; others will specify a range of e.g. Vss-0.3V to Vss+7.0V, independent of VDD. A few (most notably LCD drivers) may specify some pins as having a range like VDD-14.0V to VDD+0.3V. If a device specifies that a certain pin is restricted to the range Vss-0.3 to Vdd+0.3, then one should avoid applying any non-trivial potential to any device pins while the device is non-powered. While some devices will specify the behavior of their clamp diodes (e.g. stating that they may be safely used to source or sink up to 10mA without consequence), in other devices the geometry of the clamp diodes is such that they form parasitic transistors. For example, I saw one device where the clamp diodes on two adjacent pins would form a PNP transistor (with the base connected to VDD). If one pin was driven above VDD, transistor would conduct current from that pin to the adjacent one.

Longer ...

Use: Vdd = Vcc.

See my recent answer about protection diodes on IC pins. Each pin has a (usually) reversed biased internal "protection" diode from pin to Vdd. Removing power to Vdd will cause it to drop to close to ground potential. Voltage applied to other pins will be conducted to Vdd via the pin's diode. From there "anything can happen and something may". Results are not predictable. Some IC's can be powered that way. Some people have built circuits that have no apparent power source but which are purposefully powered by a protection diode. This can be 'fun" to do but is bad practice and unexpected results can be expected.

HOWEVER, it would be useful to know what you are trying to achieve. If it is only to get a 1 of N output selector, this can be done by using N/10 x 4017's and enabling one at a time, using one extra IC as a selector. CD4107 data sheet at [1] (below).

See block diagram on page 2 of datasheet. Pin 13 is a negative active clock enable input, pin 12 is a clock output signal and pin 15 is an active high reset line. These may be used in a number of ways to create a multi IC one of N selector. As you were intending to sequentially select Vdds you can instead just select enable and reset lines. Note that as clock enable is true-low and reset is true-high, typing clock-enable and reset together gives you a single control signal which allows counting when low and which both clock-disables and resets the IC when high. That should be enough to allow a design, but the following suggests one method.

If 2 x 4017's (MA. MB = masterA masterB) are connected in series with clock to MA clock, carryout of MA to clock of MB, then the outputs of MB will successively go high for 10 clock cycles. The MB outputs can then be used to enable slave 4017's SA, Sb Sc ... . Up to 100 outputs can be obtained this way giving 10N outputs using N+2 x 4017s.

If less than 10 x slave 4017s are used the carryout signal from the last slave can be used to reset the counter chain.

Note that MB's outputs are active high , which is the wrong polarity to directly drive either slave rest lines or slave clock enable lines. An inverter would be require from each MB output to the matching Sx clock enable line.

There are other 1 of N output IC's and other ways of doing this. If you can advise the number of outputs required and what is being driven then a better answer can be provided. A cheap microcontroller with many port pins may be the best solution. If a microcontroller is used to drive this chain other IC's may be appropriate.

A one of N IC with active low outputs would eliminate the need for inverters in the Sx clock-enable lines.

Using the output of slave Sn to reset the system to initial state risks a "race hazard". A little thought re timing of the rest pulse may be requried to ensure clean reset.

More if required ... .