I've been working on a project where an OMAP Linux SPI master interacts with 6 SPI slaves peripherals (5x A/D converters and single magnetometer).
I can set the SPI clock frequency and have experimented with 50 kHz, 100 kHz, and 1MHz.
I attached a wiring/board diagram showing length from SPI master and all peripherals. The SPI bus length (all wire lengths) away from master is roughly 970mm for my experiment case.
The problem I've found is that communication with 1 peripheral fails as I add more of the other peripherals on the bus. Even if communication gets through to the magnetometer on the far side of the bus, communication with the A/D converters on the other side fails until the magnetometer harness stub is removed and then the A/D section returns.
where it's recommended to put a RC LPF as close to any driving node, so SCLK and MOSI on master side and each of my 6x MISO/SOMI signals. I've seen similiar approach done for USB with 47pF/27R RC network. My intention is to try this on my circuit in an effort to reduce the sharp edge fast ~100nsec edge transition.
Is this the right procedure I'm following here with adding a RC LPF? This seems really shakey, is there better practice? I saw an app note from TI where they talk about extending SPI for longer bus distances, is this an appropriate solution here or my problem simply one of high frequency harmonics from the high speed edge transition? http://www.ti.com/lit/an/slyt441/slyt441.pdf