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I've been working on a project where an OMAP Linux SPI master interacts with 6 SPI slaves peripherals (5x A/D converters and single magnetometer).

I can set the SPI clock frequency and have experimented with 50 kHz, 100 kHz, and 1MHz.

I attached a wiring/board diagram showing length from SPI master and all peripherals. The SPI bus length (all wire lengths) away from master is roughly 970mm for my experiment case.

enter image description here

The problem I've found is that communication with 1 peripheral fails as I add more of the other peripherals on the bus. Even if communication gets through to the magnetometer on the far side of the bus, communication with the A/D converters on the other side fails until the magnetometer harness stub is removed and then the A/D section returns.

I've done some reading here: SPI Bus Termination Considerations and here: Short Distance Board to Board Communication

where it's recommended to put a RC LPF as close to any driving node, so SCLK and MOSI on master side and each of my 6x MISO/SOMI signals. I've seen similiar approach done for USB with 47pF/27R RC network. My intention is to try this on my circuit in an effort to reduce the sharp edge fast ~100nsec edge transition.

Is this the right procedure I'm following here with adding a RC LPF? This seems really shakey, is there better practice? I saw an app note from TI where they talk about extending SPI for longer bus distances, is this an appropriate solution here or my problem simply one of high frequency harmonics from the high speed edge transition? http://www.ti.com/lit/an/slyt441/slyt441.pdf

Thanks, Nick

A clean CLK/MISO measurement from the magnetometer

Measuring clock transition time of the CLK signal

Does this MISO line (channel#1) show reflections?  The levels don't look digital with stair case, is this reflections

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  • \$\begingroup\$ Do you have the ability to add series resistors and change the wiring ? \$\endgroup\$ – efox29 Apr 19 '15 at 4:58
  • \$\begingroup\$ Hi efox29, yes but it will be a bit dirty. My SPI master is on a SOM mounted to my daughterboard. My intention is to cut the trace for SCK and MOSI and mount a 330-ohm/47pF 0603/0805 RC for each using epoxy/glue and do something similiar on the A/D and magnetometer boards for MISO. I'll try and make the GND stub to as close as GND pad or plane I can get. Holding off on this till I hear more back but plan to try tomorrow. I don't have ability to change SPI into a daisy-chain or anything though. Wouldn't do much good anyways, boards need are at opposite ends. \$\endgroup\$ – shraken Apr 19 '15 at 5:59
  • \$\begingroup\$ How is your system with with a slower clock like 50Khz ? What is the microcontroller you are using ? \$\endgroup\$ – efox29 Apr 19 '15 at 6:51
  • \$\begingroup\$ I would suggest starting with the SCK line first before adding Rs and Cs to the other lines. After all, edges only matter on the clock line, the other lines will be more tolerant of reflections. \$\endgroup\$ – alex.forencich Apr 19 '15 at 8:23
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    \$\begingroup\$ And with this sort of an issue, it's the edge slew rate that's the problem, not the clock frequency. If you see the same problem independent of clock frequency, then the fast edges are the problem and need to be slowed down. \$\endgroup\$ – alex.forencich Apr 19 '15 at 8:25
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It's difficult to answer this without all the details, but here is a generic look at the problem which I believe may also be the more useful type of answer for this site.

Multi-node-nets should always be simulated. They are so difficult to predict. And it took about 3 minutes to see that your design was maybe not optimal.

Here is the simulation setup for the clock from the master to all the slave devices (values are just rough estimates, as would be the case if you did this before building anything):

enter image description here

And the resulting simulation plot (we ignore what is what, units etc. as it obviously is not worth building):

enter image description here

The first idea that comes to mind is a daisy chain of all the inputs and a simple parallel termination. A fly-by scheme if you want. This looks like this in the simulation setup:

enter image description here

And the result plot looks a lot nicer:

enter image description here

If you can live with the increased power consumption of the thevenin termination and the reduced voltage swing on the clock inputs of the various devices and... (only you know the actual constraints)... then some variation of this may actually be worth building.

There are other solutions that would work, but the key is to understand that multi-node nets are not easy to predict. The 5 minutes of simulation here before you build something can save a lot of time later. Unfortunately this type of simulators do not come cheap.

I am using Cadence SigXplorer here. The usual disclaimer apply: I do teach classes in signal integrity and often have Cadence or Mentor sponsor software licenses for those classes.

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  • \$\begingroup\$ What software are you using to sim transmission lines ? \$\endgroup\$ – efox29 Apr 19 '15 at 23:56
  • \$\begingroup\$ @efox29 Cadence SigXplorer and Mentor Hyperlynx. \$\endgroup\$ – Rolf Ostergaard Apr 20 '15 at 5:15
  • \$\begingroup\$ @nickishere (OP) Did this answer your question? \$\endgroup\$ – Rolf Ostergaard Apr 22 '15 at 14:55
  • \$\begingroup\$ Hi Rolf, Thanks for taking the time to simulate this circuit, really appreciate it. I'll have to look into Cadence SigXplorer and will def. look for a tool like it next time I approach this a large bus. I'm marking your answer as correct as it's the most detailed and pertinent. However, I must say I did end up using the topology empirically so I cannot say it works. \$\endgroup\$ – shraken Apr 23 '15 at 0:46

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