# Rising edge pulse detector from logic gates

The circuits I describe are entirely made of 7400 series logic gates (7402, 7404 and 7408 ic). I'm trying to build a rising (positive) edge pulse detector using logic gates.

The following circuit should work in theory: (see this)

I do not expect the short output to be seen through a LED so, to test it, I make it trigger an SR latch to its up state: However, it doesn't have effect on the latch. So I added an inductor to delay the input to the NOT gates in the pulse detector circuit and it worked: But now I can see the short flashing output through a LED which I should not because it would mean it is too long to work with a circuit like that: Which intends to toggle the D Latch output on each clock rising edge (Note that this is a D Latch not a D Flip-flop)

And anyway there is no place for inductors in integrated circuits so there must be a way to do this only with logic gates. Can someone solve this mystery?

BTW It does not show in my schematics but I did put 10K pull-down resistors where there might be floating pins.

• To where did you tie the 'R' input of the SR latch? Apr 19, 2015 at 17:44
• In your last approach with the D flip flop, what happens if you use the first pulse detector circuit? (The pulse detector without too long output) By the way, for troubleshooting circuits, using an oscilloscope will generally tell you more than using your eyes.
– Zulu
Apr 19, 2015 at 19:19
• "Rising edge pulse detector" is gibberish. What are you trying to detect, a rising edge or a pulse? Make up your mind. Aug 2, 2015 at 21:02
• Which component should I use to implement simple logical functions involving positive and negative edges? Mar 18, 2019 at 16:47

You may implement this digital design for detecting rising edge. simulate this circuit – Schematic created using CircuitLab

The output will go high as soon as a rising edge is detected on the D input. The output is cleared on the next rising clock edge. • Which component should I use to implement simple logical functions involving positive and negative edges? Mar 18, 2019 at 16:45

May be the delay generated by three not gates is less than the set up time. So you might want to check with some more odd number of not gates and this also explains why your circuit worked with an inductor

Use one Schmitt-inverter with a resistor in series and a capacitor parallel to the input, or use an even slower type of inverters.

Form what I understand you are trying to build a circuit (using on logic gates) that toggles an LED on the rising edge of the input. You could achieve this without the pulse detector circuit by replacing the D Latch with a D flip flop (which is edge triggered).

A D Flip Flop can be constructed from two D Latches and a NOT gate as shown here:

https://commons.wikimedia.org/wiki/File:Negative-edge_triggered_master_slave_D_flip-flop.svg If your schematic is correct, your problem is that you're letting the R input float. With 7400 chips, a floating input functions as a logical 1. As a result, immediately after your set pulse occurs (and it's only about 30 - 50 nsec, so you won't see it visually), the flip-flop is immediately reset.

You need to generate a normally-low reset pulse on the R input before you try to operate your circuit.

• I'm sorry my schematic is somewhat crude I did actually put all the pull-down resistors wherever necessary (clock input and SR latch). Apr 19, 2015 at 20:12
• 10k pull-down resistors are not adequate. Use a 1k pullup resistor on an unused inverter or NOR gate, and use the output of the gate as a logic 0. 7400 input current is nominally 1.6 mA, with a 0.8 volt low threshold. 1.6 mA into 10k gives 16 volts. A 10k pulldown is the same as leaving a 7400 input floating. It works (pretty well, but it's a bit high) for CMOS, but not for TTL. Apr 19, 2015 at 20:33

I suspect the parasitic cap on the input of the S/R latch is high enough that the output pulse never reaches Vhimin to drive S. I bet if you put a scope on the net connected output of pulse to S-input you would see <3V peak.

In the past I have made pulse choppers with 7400 series logic and found that the inherent gate delay (tau) of 7404 inverters isn't enough to generate a clean enough edge without an OpAmp trigger on the output (instead of an S/R latch). One solution would be to add more inverters to your pulse generator. Another would be to use a differential detector with a lower threshold and higher input impedence.

You need to create a specification for your circuit. E.g., what are the static timing characteristics of the pulse you want to detect? Is there a minimum slope, and a minimum threshold that constitutes your pulse? The circuit would look very different if your hold time is picoseconds vs milliseconds.