2
\$\begingroup\$

I have this piece of code here:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity first is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
result : out STD_LOGIC_VECTOR(3 downto 0);
clk : in STD_LOGIC
);
end first;

architecture behavioral of first is
begin
process(clk)
begin
result <= a + b;
end process;
end behavioral;  

In Quartus II, how can I tell the software that I want 'clk' to be a clock so that I can find out the maximum frequency (Fmax) at which this design can run? Whenever I compile my design I get the warning 'No clocks defined in design'.

\$\endgroup\$
  • \$\begingroup\$ For a correct Fmax analysis you need to register a, b and result or you need to add propper timing constraints. The answers below add a register only to the output (result) not to the inputs. \$\endgroup\$ – Paebbels Apr 19 '15 at 22:56
  • \$\begingroup\$ How do I properly use the keyword 'register' for these signals? \$\endgroup\$ – gilianzz Apr 20 '15 at 14:45
1
\$\begingroup\$

The problem is that you actually have no clock, or to be more precise, no clock is used. Check your process:

process(clk)
begin
    result <= a + b;
end process;

This process doesn't use the clock. You probably wanted to do this:

process(clk)
begin
    if rising_edge(clk) then
        result <= a + b;
    end if;
end process;

This code uses the clock and Quartus should report it.

Update

If this is your top-level, it won't have a fmax value for the clock because it has no register-to-register path. Your input signals a and b are not registered, thus the absence of register-to-register path. You can easily solve this:

process(clk)
begin
    if rising_edge(clk) then
        a_r <= a;
        b_r <= b;
        result <= a_r + b_r;
    end if;
end process;
\$\endgroup\$
  • \$\begingroup\$ Thanks, the software now sees that I have a clock, but how can I find the Fmax? \$\endgroup\$ – gilianzz Apr 20 '15 at 18:18
  • \$\begingroup\$ I don't have Quartus ATM on my new computer, but I think it's somewhere in the reports even if you don't specify the clock's frequency. I saw another problem in your test though, I've made an edit. \$\endgroup\$ – Jonathan Drolet Apr 21 '15 at 13:13
0
\$\begingroup\$

Your design has a signal called clk, but it isn't used as clock. You should add if(rising_edge(clk)) statements in the process body.

Once you modify your desing, Quartus will detect that clk is used as clock and you will be able to proceed with your Fmax analysis.

\$\endgroup\$
0
\$\begingroup\$

Once you have included a clock in your logic (see other answers), you could take a look at timequest, the timing tool in Quartus. You can use timequest to create an sdc file to constrain your design (or you can write one manually). It often makes sense to tell Quartus what the Fmax that you need is, as then it can have a go at achieving this.
If you have multiple clocks this is particularly important because then the tools can prioritise the stuff that needs to go faster at the expense of the less critical stuff.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.