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Although this a very specific question, I think someone of this site could give interesting information.

I am using a SFF SDR of Lyrtech enter image description here

I am trying to generate a .bit file using a .vhd file and a .ucf.

My program is very simply and it light a led and put off the others.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity oneled is
Port ( o_FpgaLed0_p : out  STD_LOGIC;
       o_FpgaLed1_p : out  STD_LOGIC;
       o_FpgaLed2_p : out  STD_LOGIC;
       o_FpgaLed3_p : out  STD_LOGIC;
       o_FpgaLed4_p : out  STD_LOGIC);
end oneled;

architecture Behavioral of oneled is
begin
o_FpgaLed0_p <= '1';
o_FpgaLed1_p <= '0';
o_FpgaLed2_p <= '0';
o_FpgaLed3_p <= '0';
o_FpgaLed4_p <= '0'; 
end Behavioral;

As you can see its a very simple program just to learning to use this board.

My question is. ¿What´s wrong, do I need one file more? Thank you for your help.

This is a link to download my constraint file. https://www.dropbox.com/s/2wlaa5asa5tprdw/sdrioring_virtex4ffg668.ucf

I have these error messages:

ERROR:ConstraintSystem:59 - Constraint <NET "i_FpgaClk_p" TNM_NET =
   "i_FpgaClk_p";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(29)]: NET "i_FpgaClk_p" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "i_PllMClkg_p" TNM_NET =
   "i_PllMClkg_p";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(32)]: NET "i_PllMClkg_p" not found.
ERROR:ConstraintSystem:59 - Constraint <NET "Top_l/ClkOpb_s" TNM =
   "100MhzOpbClk";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(49)]: NET "Top_l/ClkOpb_s" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "Top_l/ClkVpss_s" TNM =
   "75MhzVpssClk";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(53)]: NET "Top_l/ClkVpss_s" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <Net "i_nLyrio1AbInt_p" IOSTANDARD =
   "LVCMOS33";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(63)]: NET "i_nLyrio1AbInt_p" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <Net "i_Lyrio1AbReady_p" IOSTANDARD =
   "LVCMOS33";> [C:/Dropbox/Archivos sobre mi
   PFC/Files_ucf/sdrioring_virtex4ffg668.ucf(64)]: NET "i_Lyrio1AbReady_p" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
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  • \$\begingroup\$ Does anyone could add two tags more 'Lyrtech' and 'SFFSDR' (Small Form Factor Software Define Radio)? \$\endgroup\$ – Peterstone Jul 9 '11 at 15:04
  • \$\begingroup\$ Reformat you errors if you want help. \$\endgroup\$ – Brian Carlton Jul 9 '11 at 17:13
  • \$\begingroup\$ Also there isn't anything about Lyrtech, SFF or SDR in your question. Use tags about your problem, e.g. VHDL. I added the SDR tag; spelled out as this sites convention. \$\endgroup\$ – Brian Carlton Jul 9 '11 at 17:15
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The reason for all of the errors is your ucf file refers to a bunch of nets that do not exist in your simple design. You either need to:

1.) Comment out (or remove) those references from the ucf

or

2.) Include in your design all of the nets and components that the ucf refers to (and make sure they are not getting optimized out in synthesis).

Not knowing too much about your specific board I would recommend the former. In that case your ucf file will be very simple. One line for each of the 5 led ports connecting it to the appropriate pin.

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  • \$\begingroup\$ What do you mean when you said "Include in your design all the nets and components that the ucf refers to"? Where Should I include these references, in the .vhd file or in a .ucf file? \$\endgroup\$ – Peterstone Jul 11 '11 at 9:42
  • \$\begingroup\$ The point of the ucf file is to constrain what is described in the vhd file(s). You would have to describe logic for each of the nets/pins constrained in the ucf file to get rid of those errors. Or to make it easy go with suggestion 1 (also described well in Martin Thompson's answer). \$\endgroup\$ – davidd Jul 11 '11 at 20:06
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You have no clocks in your design currently.

The UCF file has three pairs of lines related to clocks which are present on the board, but if your code does not refer to them, you will get the errors you see.

Comment out those lines and that bit will be fine. Don't forget to uncomment them when you start using the clocks (and a flashing LED should be your next test :)

You also need to uncomment the lines for your LEDs, otherwise they'll be assigned to random pins, which will probably not be very visible!

Finally, when you have a bitfile, check the .pin file that is written out during the build to make sure the signals are on the pins you expected, and that you haven't missed any which are then randomly assigned. My build script has a post-PAR check of the pin file which looks for the tag that goes on unconstrained pins and ERRORs out if it finds one.

(And check that no other signals have been pushed to pins you don't want - I've had internal signals appear on external (unconstrained) pins in the past, which were connected to currently unused devices!)

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  • \$\begingroup\$ Good point on checking the pin file to make sure the constraints were applied correctly. Also it is good to make sure that no ports/pins were unconstrained and routed to an unexpected pin. \$\endgroup\$ – davidd Jul 11 '11 at 20:10
  • \$\begingroup\$ @davidd: good point - answer updated \$\endgroup\$ – Martin Thompson Jul 12 '11 at 13:06
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You can make these errors go away without commenting out unused pins in the .UCF file.

  1. Open up your design in Xilinx ISE;
  2. Left click on the Design Tab in the Implementation View;
  3. Right click on "Implement Design";
  4. Scroll down to and select "Process Properties";
  5. In the "Translate Properties" Category, check the "Allow Unmatched LOC Constraints" box;
  6. Click the "Apply" button, followed by the "OK" button.

This option allows you to use a master .UCF file for a particular FPGA board (i.e., the pin constraint file provided with the Lyrtech board) without customizing it for each design.

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