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I'm using a voltage divider to read the battery level of a wireless sensor platform using STM32L151. I'm shooting to use 20k for R1 and 10k for R2, to be under the 50k limit of the MCU's ADC peripheral.

How do I calculate the current wasted by the divider?

Originally, I was planning on using a P-channel MOSFET to enable the divider when taking measurements to reduce power consumption, but I see that MOSFETs have leakage current and raise the part count.

Can I just set the GPIO to push-pull as the ground for the divider and set it low when I want to measure and high when I don't?

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  • \$\begingroup\$ Are you powering the microcontroller (MCU) directly from the battery, or do you have a voltage regulator for the MCU's Vcc? \$\endgroup\$ – Nick Alexeev Apr 21 '15 at 0:13
  • \$\begingroup\$ Regulator. The battery is a lipo 4.2-3v, the MCU is running at 1.8v. \$\endgroup\$ – Matt Williamson Apr 21 '15 at 0:52
  • \$\begingroup\$ Consider even larger resistors for the divider, a few MOhm, and a capacitor to provide the low impedance for the ADC \$\endgroup\$ – tomnexus Apr 21 '15 at 19:08
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First thing - if the ADC is okay with 50K you can use 150K and 75.0K (the source impedance will be exactly 50K).

The current used by the divider will be 4.3V/225K = 19.1uA.

Unlike most micros, I think you can actually lift the lower end of the divider and reduce the current, if you pick a 5V-tolerant input that is shared with the ADC and use another 5V-tolerant pin for the divider control. At least that is what it looks like to me. You would set the control pin to low/output for divider operation and have the ADC input active. To disable set both pins to digital inputs.

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  • \$\begingroup\$ Can you elaborate a little more on the 5v tolerance? You're saying I can use a bigger ratio? But at 12bits it will read as 4095 until the voltage falls below 1.8v, the VREF, no? \$\endgroup\$ – Matt Williamson Apr 21 '15 at 2:57
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    \$\begingroup\$ 5V-tolerant means that when it's configured as a digital input it can go up to 5V without drawing hardly any current. So in measure mode, the pin connected to the 75K (bottom of the divider) is configured as a digital output and set to '0', so it's close to ground. The divider junction is connected to another pin, configured as an analog input to the ADC- it sits at 1/3 of the battery voltage. In non-measure mode, both pins are configured as digital inputs (with no pullups or pulldowns enabled if those are options on this MCU). Both 'input' pins float up to 4.2V-4.3V. \$\endgroup\$ – Spehro Pefhany Apr 21 '15 at 3:26
  • \$\begingroup\$ I see. That sounds like a great option. \$\endgroup\$ – Matt Williamson Apr 21 '15 at 4:37
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    \$\begingroup\$ Always verify the 5V tolerance of STM32 ADC input pins, it changes based on both port and family. Some families have NO 5V tolerant ADC inputs(e.g. STM32F303) and even the STM32L15x used by the OP has some ADC inputs that are not 5V tolerant(e.g. ADC13_IN). BTW, wither a GPIO pin is 5V tolerant or not is based on the pin inputs(i.e. it uses VDD_FT for it's input diodes and not VDD) and not wither it is configured for digital or analog (Or at least this was true of the 5 ref manuals I consulted(L1xx, F3xx, F1xx, F4xx, L4xx). \$\endgroup\$ – GB - AE7OO Nov 11 '19 at 17:06
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The simple answer is "probably don't bother." As pointed out by Sphero, your losses are tiny, and are probably going to be dwarfed elsewhere in the system.

I suggest reading Jack Ganssle's excellent report on ultra low power design with coin cells so you can see all the places where things can go wrong that you don't expect.

But, if you absolutely must disconnect this voltage divider, you have a couple options, both of which unfortunately require more parts.

  1. P-channel MOSFET switch on the high side of the divider to switch it in and out. As you pointed out, there is leakage current, but it should be very small if you choose the right FET. Disadvantage is you also need a BJT or an N-channel FET for the high switching voltage demanded by a P-channel FET.

  2. Use a very low power opamp to buffer the signal from the voltage divider. You don't end up switching it in and out, but you can make the voltage divider values very high.

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  • \$\begingroup\$ The op-amp would create a big problem if the processor is powered off while VBATT is high. When the processor is powered off, driving a low-impdance voltage into the ADC can cause all kinds of undesirable behavior. Also, it is expensive and unnecessary. \$\endgroup\$ – mkeith Apr 21 '15 at 19:07
  • \$\begingroup\$ Quick thought - if you pull the P-fets gate up to Vbat with a resistor to keep it off normally and then connect the gate to your gpio pin via a 100n capacitor. If you pull low, you'll get a finite time (dependent on the pullup) to measure the ADC but how much time does an ADC need anyway? \$\endgroup\$ – carveone Oct 31 '15 at 10:39
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How do I calculate the current wasted by the divider?

Since the battery voltage is 4.2V, the current consumed is \$I=V/R=4.2\rm{V}/30\rm{k\Omega}=140\rm{\mu A}\$.

Can I just set the GPIO to push-pull as the ground for the divider and set it low when I want to measure and high when I don't?

If your MCU was powered from the battery, then yes this would work. However, since your MCU isn't, you will continue to waste \$I=(4.2\rm{V}-1.8\rm{V})/30\rm{k\Omega}=80\rm{\mu A}\$.

I see that MOSFETs have leakage current and raise the part count.

Understand that your MCU is also built out of MOSFETs, and also has leakage current. An additional MOSFET (when off) won't substantially raise the circuit's power consumption over what it already is. As for part count, well... How much is this feature worth to you?

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  • \$\begingroup\$ Part count is not as important as low power, but if I can get both, at once, I would take it. \$\endgroup\$ – Matt Williamson Apr 21 '15 at 2:59
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Nobody has given you the best answer yet. Do it like this, with two transistors. Put a PFET on the top of the divider (between battery + and voltage divider). PFET source is connected to battery. Drain is connected to divider. PFET has pull-up from gate to source. Pullup can be around 100k or even more if you want. Connect NFET drain to PFET gate. Connect NFET source to GND. Connect NFET gate to processor VCC, or to a processor GPIO. When NFET gate is high, divider will be in operation. When NFET gate is low, divider will be disconnected from battery.

Personally, I think it is a good idea to make sure the battery sense divider does not drain the battery when the device is powered off, even if it is just 10s or 100 uA. Furthermore, the battery voltage should not be applied to the ADC input when VCC is not present, not even through a large resistor (unless this is a highly specialized input pin). So I would argue that you MUST disconnect the battery from the ADC any time VCC is not present.

If you cannot visualize what I typed, let me know and I will draw it for you.

Edit: Use BSS138 for NMOS and BSS84 for PMOS. Just a recommendation. These parts are very low cost in volume and are readily available.

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  • \$\begingroup\$ I do have some BSS138's on hand. So this is possible for me to do if I get the BSS84's. I was just reading about CMOS circuits the other day... is this one? \$\endgroup\$ – Matt Williamson Apr 21 '15 at 2:53
  • \$\begingroup\$ What does using two FET's give me vs just one? \$\endgroup\$ – Matt Williamson Apr 21 '15 at 2:59
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    \$\begingroup\$ If you use one PFET, what do you tie the gate to? The GPIO's of the processor will be low when VCC is off. So the PFET will be on, and the battery will be drained any time VCC is off. If you use one NMOS at the bottom, then when VCC is off, the ADC will be unpowered and will load the battery so the battery will drain. You cannot connect pullups to an unpowered input (unless the input was specially designed to allow it). If VCC is always on, then you don't need to worry about it. But if there is ever a case where VBAT is present and VCC is not, you need two transistors. \$\endgroup\$ – mkeith Apr 21 '15 at 19:00
  • \$\begingroup\$ Last question. If I use a single NFET at the bottom and nevsr turn off VCC am I good? \$\endgroup\$ – Matt Williamson Apr 22 '15 at 3:09
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    \$\begingroup\$ Well, this gets back to what Spehro was saying. If the inputs can tolerate 5V, then you should do what he said (use another GPIO instead of an NFET on the bottom of your divider). That will be cheapest and should work. If the inputs are not 5V tolerant, then the NFET on the bottom won't be safe, because once the NFET is off, the ADC input is effectively pulled up to VBATT by the upper resistor in the divider. The boards I design are mass-produced, sometimes in the millions, and inputs are not 5V tolerant, so I use two transistors. The ones I suggested are less than US$0.02 each in high volume. \$\endgroup\$ – mkeith Apr 22 '15 at 4:06

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