This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting confused. Essentially, the goal of this lab is to create an 8-bit pipelined adder and use an H-clock tree to provide the clock pulse to the sequential elements of the design. We'll just consider the gate/component level schematic here.
Here's what I know:
How to create the pipelined adder: use two 4-input adders (already created) and stick D-Flip-Flops (also created) in between the stages and at the inputs/outputs to synchronize the calculation. Basically, do what's shown below, but with only two stages instead of three:
How to create the H-tree for the clock. It should like like image b) below:
However, I'm unable to connect the two concepts in my mind, or even understand why the clock tree is necessary. Here's the part from the lab manual that I'm stuck on:
Use the buffered H-tree clock distribution scheme to provide clock signals to the sequential elements in your design.
How do I use the clock tree to distribute the clock signal to the flip-flops? If I have X flip-flops, do I need a tree with at least X branches, and use one branch for each flip-flop? How is using the tree different from just wiring the clock input directly to each of the flip-flops?