This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting confused. Essentially, the goal of this lab is to create an 8-bit pipelined adder and use an H-clock tree to provide the clock pulse to the sequential elements of the design. We'll just consider the gate/component level schematic here.

Here's what I know:

  • How to create the pipelined adder: use two 4-input adders (already created) and stick D-Flip-Flops (also created) in between the stages and at the inputs/outputs to synchronize the calculation. Basically, do what's shown below, but with only two stages instead of three: enter image description here

  • How to create the H-tree for the clock. It should like like image b) below: enter image description here

However, I'm unable to connect the two concepts in my mind, or even understand why the clock tree is necessary. Here's the part from the lab manual that I'm stuck on:

Use the buffered H-tree clock distribution scheme to provide clock signals to the sequential elements in your design.

How do I use the clock tree to distribute the clock signal to the flip-flops? If I have X flip-flops, do I need a tree with at least X branches, and use one branch for each flip-flop? How is using the tree different from just wiring the clock input directly to each of the flip-flops?


1 Answer 1


Part of the disconnect may be coming from the "H-Tree" clock distribution network being a physical layout concept in addition to a schematic level concept. The key part of the H-tree is that since every branch is physically similar, and has the same number of clock loads, that the actual clock skew will be minimized. Another key point is that you would include inverters even if the outputs are not used just to keep the distribution network balanced.

You need clock buffering on anything other than a small design, as each flip-flop clock pin will "slow down" the clock transition time to a point that your flip-flop runs slower and has a more ambiguous switching time. Significant clock skew in your design can cause you to pull your hair out during static timing analysis and verification.

If I were implementing this design in an ASIC, I might instruct the place and route tool to generate the clock network with a "H-tree" layout. If you have to turn in a (hand designed) physical layout, then you have a guideline to work from. If you just have to turn in a schematic... I guess show the clock buffer tree.

  • \$\begingroup\$ So by using the H-tree we basically create multiple copies of the same clock signal, and use one copy per flip-flop to reduce the clock-to-Q delay of the flip-flops since we reduce fan-out of these clock signals? \$\endgroup\$
    – wlyles
    Commented Apr 21, 2015 at 19:22
  • \$\begingroup\$ Perhaps what I don't understand is how this reduces skew time, or is even necessary to reduce skew time. How does the H tree reduce the skew times of the flip-flops when compared to directly wiring the clock? I know the total delay would be higher because you have a pretty big fanout, but wouldn't just wiring everything to have the same length from the clock origin to the clock input of the flip-flops eliminate the skew as well? \$\endgroup\$
    – wlyles
    Commented Apr 21, 2015 at 22:39
  • \$\begingroup\$ Assuming you have a big enough clock buffer, sure you could just directly wire all flip flops directly to it with matched path lengths... but that's a lot more complicated than it might first seem. You would need extra "delay" wiring near the buffer output, killing a lot of your signal routing lanes. You would have a lot higher peak currents, and difficulty routing power to such a large buffer. \$\endgroup\$
    – W5VO
    Commented Apr 21, 2015 at 22:59
  • \$\begingroup\$ If you're talking about just living with slower circuitry, then you'll have issues with your static timing library as your input clock slew rate will be below the level of characterization. You would have precision without accuracy; definitely something you don't want when you're trying to guarantee that a $100k chip will work. \$\endgroup\$
    – W5VO
    Commented Apr 21, 2015 at 23:04
  • \$\begingroup\$ Okay, I think this is starting to make more sense for me, especially after doing some more thinking in the layout domain (we have to create a schematic and a layout for this lab). I think the big hurdle was (like you initially said) conceptualizing everything as a physical layout. The way I understand it now, you essentially have to overlay your clock tree onto the design itself and put the flip-flops at the ends of your tree. The tree is essentially a way to distribute the clock to different places on the layout at approximately the same time (i.e. minimizing skew time) \$\endgroup\$
    – wlyles
    Commented Apr 21, 2015 at 23:18

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