I'm working on a problem that asks me to design an 8 x 3 memory chip given 2 4 x 3 memory chips. I'm not sure how to approach this problem. I've looked at the textbook and found various online powerpoints, but I'm still clueless. It would be nice if someone were to point me in the right direction to get me going. Thanks

The 4 x 3 chip: Pulled from Structured Computer Organization by Tannenbaum

What I came up with: 8 x 3 memory chip using two 4 x 3 chips

There was the restriction that there must be three input/output lines and that we may want to use non-inverting buffers to accumulate the outputs. Is my result correct? Thank you.

  • \$\begingroup\$ Did you try putting them together? \$\endgroup\$ Commented Apr 21, 2015 at 21:40
  • \$\begingroup\$ I'm not sure what "putting them together" means, sorry. I just started learning about circuits last week and now I have to design an 8 x 3, and I'm trying to learn as quickly as I can \$\endgroup\$
    – VN1992
    Commented Apr 21, 2015 at 21:45
  • \$\begingroup\$ Is that 8 bit x 3 word, or 8 word x 3 bit? If it is the former it is dead easy, if it is the latter you'll need to use multiplexers and decoders. We'd need to know more about the specific memory (what signals it has) to say more \$\endgroup\$ Commented Apr 21, 2015 at 21:46
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    \$\begingroup\$ Take a look at this post: How to design a Design a 32 x 4 memory using two 16 x 4 RAM chips. Not an exact duplicate but should give you some ideas. \$\endgroup\$
    – tcrosley
    Commented Apr 21, 2015 at 22:30
  • \$\begingroup\$ 8 bit x 3 word. Also I looked at the link, but still couldn't visualize it very well. Any additional hints would be great. Thanks \$\endgroup\$
    – VN1992
    Commented Apr 21, 2015 at 22:46

2 Answers 2


If the requirement is 8 bit by three words, it sounds as if the word size is 8 bits (the data), and there are three individual location for that data (the address).(This address range is unusual in practice, but theoretically there is nothing to prevent it).

Using your 2 four bit by three word devices, you must 'address' the words (you will have some address inputs somewhere). You should connect the addresses together on your two devices. This forms what is known as the 'address bus'.

The two individual 4 bit data should go to separate connections for your 8 bits of data. This forms what is known as the 'data bus'.

This means you will address the same location in each device at all times, with half the data from/to one device and the other half from the second device.

Changing the address changes which word you can write or read.



  • \$\begingroup\$ You suppose the questioner wants an address range that is not a power of two. That is so "unusual in practice" that you should reconsider the assumption. \$\endgroup\$ Commented Apr 24, 2015 at 23:26

The number of storage locations in a memory chip is 2 raised to the power of the number of address wires. Your 4 bit x 3 word chips therefore contain 2^4 = 16 locations (addresses). You want an 8 bit x 3 word design. This will have 2^8 = 256 addresses. You must provide: 1. A 16-output binary decoder for 4 of your address inputs. 2. Quantity 16 of 4x3 chips. Address them all in parallel by the remaining 4 address inputs. 3. Output enable logic for each chip; the 3 word output of only one chip is enabled by a line from the decoder. In TTL families a common way of selectively enabling chip outputs is by open-collector outputs with pull-up resistors. (By "8 bit x 3 word" do you mean 3-bit outputs or by "word" do you mean something wider with more bits? It doesn't affect the answer about addressing.)


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