I am researching memristors, and one application that's frequently cited is a crossbar latch that sandwiches memristors between two layers of wires to form a grid. In most examples, this is configured as a half adder. I've included an image from Wikipedia below and here is a link to a relevant HP patent with more illustrations.
From the patent, I get that there is some sequence of voltages applied to the wires that lock in values, then pass them on. However, I can't understand what exactly is happening. I'm familiar with half adders made of simple logic gates: 1 XOR with 1 AND gives Sum and Carry outputs. Could someone please explain the crossbar latch half adder in a similar context?