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Why when you synthesise some of the IP provided by the FPGA manufacturers, you end up using huge amount of resources? For example Altera's DDR RAM controller synthesises on 5386 logic units on Cyclone iv. This seems absolutely enormous to me.

I have observed this for other IPs as well. Why is that? I reckon I can design most of them in less logic, which I have done for some functions before.

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closed as primarily opinion-based by The Photon, Leon Heller, PeterJ, nidhin, Daniel Grillo Apr 23 '15 at 10:48

Many good questions generate some degree of opinion based on expert experience, but answers to this question will tend to be almost entirely based on opinions, rather than facts, references, or specific expertise. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Do it and compare. \$\endgroup\$ – PlasmaHH Apr 22 '15 at 21:08
  • \$\begingroup\$ I've done it for some functions. The end result is something like 20 times less logic. On the other hand, there shouldn't be such a huge difference. I can accept 20% but 20 times is just too big a difference. \$\endgroup\$ – user2534517 Apr 22 '15 at 21:10
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    \$\begingroup\$ Do your functions implement exactly the same thing, or is theirs maybe a very generic one with more features and you specialize it for your applications? \$\endgroup\$ – PlasmaHH Apr 22 '15 at 21:24
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    \$\begingroup\$ This is an interesting question, but not well suited for the Q&A format. It would be a good topic to bring up in chat or on a more discussion-oriented forum like AllAboutCircuits or Reddit's /r/askelectronics. \$\endgroup\$ – The Photon Apr 22 '15 at 21:24
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    \$\begingroup\$ Many logic comes from corner case handling. Questions one could ask: have you implemented powerdown, resets, cross-clock and all commands of a protocol, does your design handle errors and recover from them ... Building a working solution is simple but a solution that is standard conform ... Worst case: implementing a IP for different protocol versions. \$\endgroup\$ – Paebbels Apr 22 '15 at 21:46
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Some factor that makes IP larger than what you can design:

  • IP from vendors are feature-rich. Even if you use a fraction of the features of an IP (through GUI configuration), they are designed to support many features and architectures which unfortunately cost on the area-side. Take your DDR example, you could design it to support only 1 burst length and save logic that way, but you can't do that for an IP with a more general use case.

  • They are optimized for speed and throughput. From what I've seen, lot of care is taken from vendors to ensure fast critical path. They will also register inputs/outputs and use FIFO as buffer on interfaces. It's fine if you need it in your application, otherwise it's lost space.

  • Nowadays, they use a standard bus like AXI or Avalon to program the core's registers. The interface is huge and can be larger than the functionality for smaller core! I use a scaler core on Xilinx, the AXI version uses 50% more logic than the former version which exposed all registers as ports!

In the end, you can do smaller if you target a specific design's need, but if you need something general, robust, feature-rich and easy to incorporate in an IP-subsystem you have to pay the cost of it!

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