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I was looking at Freescale's KE02 processor family, and the MCU designers made an interesting design decision revolving around the ADC that I can't completely wrap my head around.

The KE02 has an internal bandgap reference, but it cannot be used as the reference for the ADC. Instead, the ADC reference is set to VREFH/VREFL, and the bandgap reference is tied to an ADC channel. From the datasheet: enter image description here

As for adding an external VREF, the data sheet states that VREFH/VREFL is tied to AVDD/AGND in certain packages. From what I've seem, with the exception of the highest pin count package, all other KE02s have VREFH/VREFL tied to AVDD/AGND.

24.2.3 Voltage Reference High (VREFH) VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to VDDA. If externally available, VREFH may be connected to the same potential as VDDA or may be driven by an external source between the minimum VDDA specified in the data sheet and the VDDA potential (VREFH must never exceed VDDA).

If the AVDD/AGND rail is accurate and stable, using AVDD/AGND as the ADC reference isn't an issue. However, if AVDD/AGND is tied to a noisy rail (think EMI, SMPS, etc.), an inaccurate one (e.g. rail regulated to +/- 4%), or to a non-regulated rail (think direct connection to a battery), the ADC readings become unreliable.

In such situation, the solution would be to explicitly capture the analog value of the Internal Bandgap and apply some non-linear scaling in function of the acquired value. This is a lot of extra work, especially since this would be a non-issue if the Internal Bandgap or an external bandgap were made available to the ADC's reference voltage.

So why would Freescale design the ADC this way? There's already an internal bandgap reference on the die: would it be so hard to provide it as a possible source for the ADC reference? Are there cost/yield benefits of not tying the internal bandgap reference to the ADC reference?

Or am I missing a really simple trick to calibrate the ADC readings in function of the measured bandgap voltage which would make this ADC HW implementation a non-issue?

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  • \$\begingroup\$ Maybe I'm missing what your point is. The way I see it is that you can use the internal reference to "power" the external reference pins but AD23 cannot be used as an ADC input when you opt for this. If you need AD23 as an input then the internal reference goes nowhere and is unavailable. \$\endgroup\$ – Andy aka Apr 22 '15 at 21:25
  • \$\begingroup\$ ST does the same annoying thing on some of it's mcu's \$\endgroup\$ – Mike Apr 22 '15 at 21:30
  • \$\begingroup\$ @Andyaka: Said differently, I want 0x0FFF (for a 12 bit ADC) to be == the internal bandgap voltage, always, for all values of AVDD, which this architecture cannot support. It's not terribly difficult to do this (<$1 PICs support this), so I'm trying to figure out the engineering reason behind Freescale's decision to architect their ADC without a connection from the internal bandgap to the ADC's reference. \$\endgroup\$ – TRISAbits Apr 22 '15 at 22:20
  • \$\begingroup\$ @Mike: Yeah, I see this kind of ADC architecture sprinkled here and there. I picked the KE02 because it's the latest datasheet I've been looking at. Really I'm trying to find a Cortex-M0(+) replacement for the PIC16F1823, but that's a story for another day. \$\endgroup\$ – TRISAbits Apr 22 '15 at 22:22
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This is becoming a fairly common practice with some manufacturers. Even some Microchip PICs do this (PIC10F322, If I Recall Correctly).

They do it this way because it's easier for them and not all that much harder for you. And this technique can work well - IF the Vdd rail is reasonably constant over the time period between calibration cycles.

If you think about the relationship between a measured, accurate reference voltage and the A/D reference varying, you will see that as the A/D reference voltage (Vdd) drops, the apparent reference reading will INCREASE.

That's okay, if Vdd comes from an unregulated battery supply that slowly changes. It's not so good if you require really accurate readings and your power supply is noisy.

Note that it's also okay if you are doing primarily ratiometric readings such as those coming from some form of bridge-type sensor (strain-gauge, pressure sensor, etc).

Many times with that sort of product, all you need is low-battery indication. You don't need to do any run-time calculations - simply read the internal reference and signal battery status depending upon whether the A/D reading is above or below some value that you calculated when writing your code.

For many simple battery-powered products, this technique is just fine. If you require a better A/D converter, either use a different chip or add an external A/D converter with it's own reference.

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  • \$\begingroup\$ "or add an external A/D converter with it's own reference." This is key - if the largest pin number package is overkill, to get access to VREF, then the solution would be a small external ADC chip with whatever custom analog references you need. Can also make PCB design better too, having the ADC chip with it's own plane and traces, away from the digital switching MCU. \$\endgroup\$ – KyranF Apr 22 '15 at 23:43
  • \$\begingroup\$ Would it then be safe to assume that ADCs are architected this way to save on cost? \$\endgroup\$ – TRISAbits Apr 23 '15 at 3:55
  • \$\begingroup\$ The more I think about this, the more it strikes me as odd that a microcontroller advertised for robust applications would not have a reference of any sorts tied to the ADC reference. From the website: "The family is next generation MCU solution with enhanced ESD/EMC performance for costsensitive,high-reliability devices applications used in high electrical noise environments." I suppose that in order to get accurate readings with this MCU one would want to have a high accuracy low ripple regulated rail and a good AVDD filter, which adds cost. Maybe I'm making this a bigger deal than it is. \$\endgroup\$ – TRISAbits Apr 23 '15 at 22:10
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I believe the biggest reason for this design decision is that the bandgap wouldn't be acceptable as reference voltage to the ADC used without costly modifications, either because of the current requirements of the DAC (AVDD seems to feed it directly, no buffers involved), or because at 1.25V the comparator in the ADC would have to be more accurate (according to the KE02 datasheet, VDDA should always be between VDD-0.3V and VDD+0.3V, so it will be at least 2.4V). This is just me speculating the design decisions though.

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