I've started designing an implementation of an 8088 from scratch with the goal of being cycle-exact. I can understand the reasoning behind the number of clock cycles for most instructions, however I must say I'm quite puzzled by the Effective Address (EA) calculation time.

More specifically, why does computing BP + DI or BX + SI take 7 cycles, but computing BP + SI or BX + DI take 8 cycles? Note that this is the number of cycles for the whole EA calculation, which includes a shift plus add with a segment register (presumably this takes a couple of cycles to keep combinational delays as low as possible).

I could just wait for a given number of cycles in my design, but I'm really interested in knowing why there's this 1-cycle difference (and overall why it takes so many cycles to do any EA calculation, when an ADD between registers is just 3 cycles).

  • \$\begingroup\$ I assume you got the timings from a manual or data sheet.Could you link to the source please, just so we're all on the same page? \$\endgroup\$ – drxzcl May 5 '15 at 22:04
  • \$\begingroup\$ Correct, I used the Intel 8086 Family User's Manual from 1979, you can find it here for instance: matthieu.benoit.free.fr/cross/data_sheets/… \$\endgroup\$ – Matthieu Wipliez May 6 '15 at 7:33
  • \$\begingroup\$ Possible duplicate questions here... stackoverflow.com/questions/29842659/… \$\endgroup\$ – bigjosh May 6 '15 at 16:47
  • \$\begingroup\$ I know I asked the question there as well, thinking that maybe people with a different background might have a different answer :-) \$\endgroup\$ – Matthieu Wipliez May 7 '15 at 8:45
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    \$\begingroup\$ Great question (and noble project)! Hopefully some former Intel person can shed some light. Otherwise I think the only other way to know is spend a summer staring at the die... \$\endgroup\$ – bigjosh May 11 '15 at 2:44

Gracious reply from Stephen Morse (designer of the 8086)...

Boy, you are really asking a question from my deep distant past. The answer obviously has to do with the way the addressing modes were micro-coded, and the person who wrote the microcode (Jim McKevitt) is no longer alive. So I don't know how you can get an authoritative answer.

A definitive answer may have to wait for someone to reverse engineer the silicon...

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  • \$\begingroup\$ Given the age of the 8086, I suspected that this was a possibility [that designers might not be alive anymore]. Thank you for your efforts to answer this question, this is well worth the +50 bounty. Thanks also to Stephen for the information; and rest in peace Jim McKevitt. \$\endgroup\$ – Matthieu Wipliez May 11 '15 at 14:43

I would say this have something to do with the internal bus. BP+DI or BX+SI does not require a piece of data to cross from one internal bus to another but the other way around requires so. This is when the processor have to spend one more cycle to let the bus settle down.

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