Radix-4 multiplication problem with unknown simulation output

Question

I'm writing code in Verilog that takes A and B as 8-bit inputs and multiplies them using the radix-4 method.

When I execute the code, the shft output appears as "xx0", and mutipler can't take the value of the input A.

Can any one help me with that?

This is the sub-code:

module pha1 (A, B, M ,clk, shft);
  input wire [7:0] A, B;
  input clk;
  output reg [7:0] M;
    
  reg [7:0] mutipler;
  
  output reg[2:0] shft;

  reg init;

  initial 
    init=1'b0;
  initial 
    mutipler=A;
  
  always @(posedge clk)
  begin
    shft = {mutipler[1], mutipler[0], init};
  end 
endmodule

This is the testbench :

`timescale 1ns / 1ps

module pah1tst;
reg [7:0] A;
reg [7:0] B;
reg clk;
wire [9:0] M;
wire [2:0] shft;

pha1 uut (
    .A(A), 
    .B(B), 
    .M(M), 
    .clk(clk), 
   .shft
);

initial clk = 0;
always #2 clk = ~clk;

initial begin
    A = 2;
    B = 5;
    #5;
    #34;
end
endmodule

Answer 1

"initial" only happens once at time zero. Try:
assign mutipler = A;

Better yet, why not just use A directly.

Use non-block assignment for clocked logic (less likely to get unintended behavior):
shft <= {mutipler[1],mutipler[0],init};

In general, implement reset for clocked logic so you can force known states at start of simulation.

(By the way I don't know radix-4 multiplier.)

Answer 2

You only assign mutipler once at time 0 in the initial block. Since a reg always initializes to X (the unknown value in Verilog), the initial value of mutipler will be 3'bxxx. You do assign it the value of A at time 0, but A is also likely to have all X, too.

Do you really need mutipler, or can you just use A as follows?

always @(posedge clk) begin
    shft <= {A[1:0], init};
end