I heard that Stitching capacitors are used to provide shortest return path whenever a signal is routed along the 2 power plane splits. As we know the return current path will be right under the trace. So how does the stitching capacitor provide shortest return path? As we already know that capacitor blocks DC current. So when I connect a stitching capacitor, how does return current flows through the capacitor?
We're only talking about high frequencies here. If there is a DC connection, then there would be no need to split a plane. If you split the plane there is a loop created that has some area. That means there is inductance in the return path and a voltage can appear if the current changes suddenly (as when a signal switches). That's undesirable- it upsets the signal and emits EMI, and the reason why (rule of thumb) you should not pass a signal trace over a split in a plane if you can avoid it.
If you cannot avoid it, then the next best thing is to make the plane appear to be one contiguous sheet of copper to high frequencies- by stitching capacitors across the trace near (say on either side) of the signal trace.
Similar issues will occur with signals piercing multiple internal planes.
Initially, I thought it was a bit like this circuit:
But then I found information here: http://www.hottconsultants.com/techtips/pcb-stack-up-6.html. From what I gather, stitching capacitors are only to reduce EMI etc, so it doesn't come into play for DC. So as far as I can tell, it acts as a coupling capacitor. So something like this:
Perhaps someone can confirm? The source I linked to mentions inductances which my diagram doesn't touch on, but perhaps it's the same principle?
A good read...
Splitting a plane is done to permit more than one voltage or ground return region to be used on a single layer. For example, you could have 5VDC, 3.3VDC, 12VDC, and 1.2VDC all on the same layer by splitting the plane into isolated regions of copper for each voltage. Likewise, you could have an analog ground region on the same plane layer as a digital ground region by splitting the copper into isolated regions.
Each EDA package has its own way of defining the net assigned to a split plane region. It depends on what software you are running.
The "rules" for split planes really are design considerations for the signal layers that are adjacent to the planes. For example, you want to avoid routing a signal trace over the void between splits - it creates a discontinuity in the trace impedance that has to be compensated for with bypass capacitors. You want to avoid running a signal trace over a split that is unrelated to the signal (for example, you wouldn't want to run an analog signal trace over a region of digital ground returns, or a sensitive signal over a split used to supply power to relays).
You can have splits on as many plane layers as you want. Just keep in mind the signal sensitivities noted above. Also remember that the splits on different plane layers that belong to a single net have to be connected together such that you have a sensible current flow from source to sink. All of that copper couples to nearby board structures capacitively - you need to be sure that you control that coupling to protect signal integrity and prevent EMI.