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Can all Cortex M0/M3 cores do this?

LDRH r0, [0x8001]

This would suggest yes but I don't see anything specific about Cortex-M cores.

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1) As the Cortex-M instruction set doc suggests, the construct in your example does not comply with the syntax. The second operand should be a register with optional immediate offset.

2) As the instruction restrictions state, the computed address should be divisible by the number of bytes in the transaction. In your case it's a half word, therefore divisible by two.

3) Generally (for Cortex-M0), this page is stating that:

An aligned access is an operation where a word-aligned address is used for a word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to perform an unaligned memory access operation results in a HardFault exception.

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