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I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd.

My code:

library ieee;
use ieee.std_logic_1164.all;

entity first is
port(
PC: in STD_LOGIC_VECTOR(7 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0);
clock : in STD_LOGIC
);
end first;

architecture behavioral of first is
begin 

rom_inst : rom PORT MAP (PC, clock, data);  

end behavioral;

I get the error: Error (10482): VHDL error at first.vhd(15): object "rom" is used but not declared

How can I fix this problem so VHDL recognizes that I have a ROM in my external file named ROM.vhd?

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  • \$\begingroup\$ You likely need to use it, in the same way you use any other entities declared in other files. \$\endgroup\$ – David Apr 25 '15 at 12:21
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You have two solutions, the first is to use components to define rom, place this code in your architecture's declaration, between architecture and begin.

component rom is
port (
    PC: in STD_LOGIC_VECTOR(7 downto 0);
    data : out STD_LOGIC_VECTOR(7 downto 0);
    clock : in STD_LOGIC
);

The second solution uses VHDL-93 syntax instead. Simply replace your instantiation with:

rom_inst : entity work.rom PORT MAP (PC, clock, data);

I prefer this syntax, but components are more flexible. You need components when instantiating block from Verilog, an IP core or a netlist. Components can also be binded differently trough configuration blocks.

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  • \$\begingroup\$ Just realized you used a megafunction. The second technique only works with vhdl files that are in your project. \$\endgroup\$ – Jonathan Drolet Apr 25 '15 at 13:21

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