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enter image description hereThis question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock on my nexys4 DDR board and multiply it by 2. Can this be simply achieved using the .xdc constraint file? I have tried using the clocking wizard IP but perhaps I simply don't understand how to instantiate the clock with respect to my source design. I have attached a few pertinent captures to better explain my issue. Any help on this would be greatly appreciated.

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No, you can't.

The .xdc doesn't control the design, it informs the tool of the physical reality of the board. Setting the clock to 100MHz or 200MHz doesn't change the design in any way, the tool will always verify that your design works with the constraint you inputted. If you forget to input constraint or input wrong constraint, you get in a situation where the tool tells you the design works when it doesn't (or vice-versa).

You have to use the clocking wizard. The input clock to the clocking wizard comes from an oscillator on the board (or another clock generated by a clocking wizard), in your case the 100MHz oscillator clock. You set the wizards's parameter for the desired output clock frequencies (2x time input clock), and voilà!

There are several reference design for your board, you should look at them to see how the core functionalities works.

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  • \$\begingroup\$ thank you for the reply. I actually have done a little more than just altering the .xdc via create_clock commands. My process was: 1) Create a custom IP of simple SVGA controller 2) Use Block design to link clocking wizard with SVGA Block and connecting the external pins to the appropriate pins I referenced in the .xdc 3) create .v from extrapolated instantiation template from the RTL 4)refresh hierarchy and finally compile. The whole thing goes through and says it is driving the load at the correct speed but in actuality nothing is happening. \$\endgroup\$ – Blake Thompson Apr 26 '15 at 6:07
  • \$\begingroup\$ Did you simulate it? \$\endgroup\$ – alex.forencich Apr 26 '15 at 7:20
  • \$\begingroup\$ No, I haven't yet, seems like the likely next step though. I'll write a testbench and see what I can. Thanks for your reply \$\endgroup\$ – Blake Thompson Apr 26 '15 at 23:23
  • \$\begingroup\$ A SVGA block is pretty complex, your problem could be anywhere. If you are not sure about your clock, isolate the problem. For example, you can make a counter that toggle a led every 200e6 clock cycles, or simply output the clock and measure it's frequency on an oscilloscope. If Xilinx report for working clock as 200Mhz, it means you probably connected the clocking structure properly. \$\endgroup\$ – Jonathan Drolet Apr 26 '15 at 23:28
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Not to my knowledge. Generally what you need to do is specify the input clock frequency in the constraints file, then instantiate the necessary clock management/PLL components to synthesize the new clock frequency. The constraint for the internal clock should be generated automatically by the tools.

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