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"Obtain an 8 X 1 multiplexer with a dual 4-line to 1-line multiplexers having separate enable inputs but common selection lines. Use a block diagram construction."

This is a question i came across recently . now the doubt i am having here is that can we just implement it by assuming that mux has a enable pin .I mean is there any other way of implementing it .

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Not really. You either need enable pins on the MUXes, or you need a 2 to 1 MUX on the output. Seems like the problem statement explicitly mentions enable lines, so that's probably the solution they're looking for. If you are targeting a particular architecture (e.g. FPGA) then one of these may make more sense. For instance, you can't do tristates within an FPGA, so you would need to use a 2 to 1 mux. On an ASIC, you might be able to use a tristate, but you could pay for it in timing performance. With discrete TTL logic, tristate is probably the simplest implementation if the muxes have output enables.

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