I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem).
I have managed to generate the IP, but I don't understand which clock should be used for the Avalon-MM interface.
I have looked at a sample design which uses Qsys, the
avl_0 bus is marked with
associated clock = mp_cmd_clk0, not the clock used by the NIOSII CPU, which is
pll_ref_clock used by the memory controller's PLL.
As my design only uses VHDL, no NIOS nor any other Altera IP, I would like to avoid Qsys for wiring the blocks together.
What is the reference clock for the Avalon bus ?
afi_half_clk, something else ?
Can I choose the frequency, or is it a fixed ratio based on the DRAM datarate, the bus width ?
(As comparison, the Xilinx MIG DRAM controller has internal FIFOs, clocks are inputs and can have any frequency)
I have eventually found some relevant information.
Volume III, Chapter 4 : Hard Memory Interface.
The Avalon bus[ses] are managed by the "Multi-Port Front End (MPFE)"
The Avalon busses are associated with the mp_cmd_xxx_clk, mp_rfifo_xxx_clk, mp_wfifo_xxx_clk signals, and there is some internal resynchronisation in the memory controller so that any clock can be used : "The MPFE handles the clock crossing between user logic and the hard memory interface."
Not all Altera FPGA families seems to have that feature available, or they use different controllers. This Altera DRAM controller for Cyclone V has finally very similar features to the Xilinx MIG IP.