I have implemented a UART receiver/transmitter (8-bits) in VHDL for use on a Digilent Nexys 3 FPGA. So far I have managed to read inputs in a FIFO, process each byte individually and write the output byte-by-byte to another FIFO for transmission.
What I ideally would like to do is read the consecutive inputs from the UART module in a std_logic_vector register instead of a FIFO. The number of inputs I am working with is always constant e.g. 4 inputs x 8 bits each = 32 bits. It would go something like this:
inputs in hex (not ascii - sent with e.g. RealTerm): 01 02 03 04 my_reg std_logic_vector(31 downto 0): X"01020304"
I have considered reading out the values of the input FIFO to a register once the FIFO is full, but that would waste resources on my board for the FIFO. Is there a way to do this on the fly, as the UART input values come in?