I have implemented a UART receiver/transmitter (8-bits) in VHDL for use on a Digilent Nexys 3 FPGA. So far I have managed to read inputs in a FIFO, process each byte individually and write the output byte-by-byte to another FIFO for transmission.

What I ideally would like to do is read the consecutive inputs from the UART module in a std_logic_vector register instead of a FIFO. The number of inputs I am working with is always constant e.g. 4 inputs x 8 bits each = 32 bits. It would go something like this:

inputs in hex (not ascii - sent with e.g. RealTerm): 01 02 03 04
my_reg std_logic_vector(31 downto 0): X"01020304"

I have considered reading out the values of the input FIFO to a register once the FIFO is full, but that would waste resources on my board for the FIFO. Is there a way to do this on the fly, as the UART input values come in?

  • 2
    \$\begingroup\$ Have you considered having a 32bit wide register, group the enable pins into 4 groups of 8 bits, and then use a counter/decoder to select which group is enabled - after all 4 are loaded, copy the data into another 32bit register ready to be read while the next set of 4 is being loaded? \$\endgroup\$ Apr 27, 2015 at 4:51
  • \$\begingroup\$ Yeap I tried that but it still gets quite complicated, I was wandering if there is a more intuitive way that I'm missing \$\endgroup\$
    – koukouviou
    Apr 27, 2015 at 17:56

1 Answer 1


To do this properly, you need to implement some sort of framing protocol with a state machine. I recommend cooking up a basic packet format that at least has some sort of magic number identifier in the header that the state machine can look for. This is used to discard any extra bytes that might be received due to line noise, etc. The state machine looks for that (might ended just be one byte), discards it, and then stores the following bytes into the correct locations in the output register.


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