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I have a reset signal which should be triggered by a falling flank from 5V to 0 volt. This flank should generate a low pulse (5V -> 0V -> 5V). This can be done by just adding a capacitor and a pull-up. However since I also use the RESET pin for debug wire I can not have a capacitor. So what I need:

Input: falling flank from 5V to 0 volt Output: not conected -> 0V -> not conected

Outside this circuit I will have a 20k pull-up to the RESET pin. The important part is that there may be no low pass filtering by caps on the reset pin since that will afect the debug wire.

How do a low cost circuit look for this?

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Use an AND (assuming negative RESET!) or OR (for positive RESET) gate to combine the signal used for the debugging interface with the one used to for the usual RESET function.

Or use open-drain buffers with wired-AND connections.

For better control of the RESET pulse, use a one-shot like SN74LVC1G123 instead of just an RC circuit for the reset function.

None of these chips should cost more than a few dimes in volume, or a dollar or so onesy-twosy.

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  • \$\begingroup\$ Thank you. I want to minimze footprint and now ha e different ways to go as I want to. \$\endgroup\$ Commented Apr 28, 2015 at 4:38
  • \$\begingroup\$ In the end I decided to go with an low active open drain 3 pin sot with an activation level 2.5 volt. \$\endgroup\$ Commented Apr 28, 2015 at 12:53

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