# Restrict area trouble in Eagle

I am trying to get a small section of my PCB design to be ground-free as this is the advised layout given by the manufacturer of the component.

However, I believe that because there are components within this restrict area that are, or need to be, connected to GND, the restricted area fills with a ground plane that I do not want. Below are some related images.

The red line indicates my desired restrict area. Ideally I would like this area to be free from the surrounding ground plane and I will route the components that are required to be connected to ground manually with a few tracks.

Alas this does not happen and below is the actual result I get once I have 'ratsnested' the design.

As you can see, the area has indeed filled in with the ground plane, although it is a separate one to the main one, it is still an issue. So I would like it not to fill in at all!

Is it possible to do this on Eagle?

I need it because it is what the manufacturer recommends for the layout and it has proved problematic already without following there guidelines so I would like to rule out any possibility for problems in the future.

• Maybe this will be helpful."Restrict polygons make sure the specific copper layer cant be placed within the polygon. " – Bence Kaulics Apr 28 '15 at 10:43

## 2 Answers

After you draw the polygon dont name it GND or what ever that is the same net as the ground of the components.

On the properties window (right click on the polygon) -> Properties -> Polygon Pour -> Cutout. The should clear the copper inside the polygon and allow you to still draw tracks.

• By the way name of the polygon doesnt make a difference on the cutout behavior – Dersu Uzala Apr 28 '15 at 11:25
• Can you guys tell me how to make the default starting window size bigger? When I open eagle, the windows (schematic, board and config, all of them) are small and I have to manually expand them every time. – Whiskeyjack Apr 28 '15 at 13:08

Just draw a polygon in the 'Restrict'-layer. This will prevent EAGLE from placing any copper there automatically. The following picture shows an IC placed within a GND plane. All pins (except one) are connected to GND in the schematic, and a polygon is drawn in layer tRestrict. A ratsnest calculates the GND polygon, and as you can see, EAGLE does not do anything inside the restrict-polygon. It is still possible to draw tracks by hand, as I did.

However, this leads to some DRC errors, which you have to accept/ignore.