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I am new to advanced integrated circuits as it is my first course on the subject and there was a discussion about geometrical scaling in the seminar. The discussion proceeded with the fact that geometrical scaling has its limits because after a certain time leakage current(read tunnelling) through the MOS dielectric at the gate becomes high enough to override the reason we switched from BJTs to FETs in the first place(reduction of power consumption by switching from a current controlled source to a voltage controlled source). Hence, they inferred, the semiconductor industry started using High K materials. But High K simply means a higher dielectric co-efficient. What has High-K got to do with subjugating tunnelling infused leakage? When I last learnt about tunnelling, schrodinger's wave equation never featured any term for di-electric constants??

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  • \$\begingroup\$ The wikipedia page on this is quite good: en.wikipedia.org/wiki/High-%CE%BA_dielectric - basically it allows an equally effective gate with a thicker, less leaky layer. \$\endgroup\$ – pjc50 Apr 29 '15 at 9:40
  • \$\begingroup\$ It does not answer the question, I understand that with decreasing transistor feature sizes the capacitance decreases, so high-K dielectrics are used, but how does it effect power consumption from the tunnelling perspective? The tunneling current for sub 2nm dielectrics will be exponentially high. Are we even manufacturing sub 2nm dielectrics, last I heard was that we were limiting the insulation thickness to 4nm. \$\endgroup\$ – ubuntu_noob Apr 29 '15 at 10:13
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High-K in-and-of itself does nothing to mitigate tunneling. What it does is ENABLE the use of thicker gate oxides in MOSFETs for the same (or improved) performance. A thicker oxide reduces tunneling current exponentially, as you said.

I think one point that will help you understand is that the drive current of a transistor (MOS) is proportional to the oxide capacitance. The equation is:

Iout = uCox*W/L(vgs-vt)^2

Cox is the unit oxide capacitance of the transistor. Making the dielectric thinner (keeping the same oxide) is one way to improve drive current, and is a key part of scaling (reducing device length is another). The problem happens (as you noticed) when you get the oxide so thin you get a lot of tunneling current in the gate.

The capacitance between two conductors is proportional to the dielectric constant and inversely proportional to the distance between the conductors. Therefore, to increase Cox and increase performance you must either decrease the distance between the conductors (i.e. use a thinner gate oxide) or increase the dielectric constant. Thinning the oxide beyond a certain point is self-limiting due to tunneling-induced leakage. To get around this you can use a high-K dielectic. Simple as that.

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  • \$\begingroup\$ Ohkayyy...!! I got it now, So basically high k enables you to apply thicker oxides and prevent the capacitance from decreasing and that in turn balances the channel current and allows for prevention of gate leakage. Great...!! \$\endgroup\$ – ubuntu_noob Apr 29 '15 at 21:13

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