1
\$\begingroup\$

In CMOS technology, why does the substrate always have to be p doped? When we need a p-channel MOSFET, we generally create an n-well into it and create p source and drain regions. Why does the balance have to work that way, why not the other way round?

\$\endgroup\$
3
  • \$\begingroup\$ Where did you read that? \$\endgroup\$
    – Golaž
    Apr 29, 2015 at 10:10
  • \$\begingroup\$ Please correct me if I'm wrong. That's the structure they're using at the fabrication lab that I'm concerned with. Do we also use n-doped substrates? \$\endgroup\$ Apr 29, 2015 at 10:16
  • \$\begingroup\$ Sorry I missread your question. \$\endgroup\$
    – Golaž
    Apr 29, 2015 at 10:37

1 Answer 1

1
\$\begingroup\$

There is no rule that mandates a P-sub/N-well process. In fact, there are many CMOS processes which work the other way, with N-sub/P-well. An example of a chip that uses such a process is the LMC660. A look at its schematic emphasizes this: the NPN's Q26/27 in its bias circuit are constructed as lateral N+/P-well/N+ (with a parasitic vertical substrate collector tied to \$V_{DD}\$).

As far as CMOS IC design goes, the primary impact is to determine which devices (between NMOS and PMOS) can have wells at different potentials.

As you probably know, a P-well should be more negative than the N+ source/drain diffusions of the NMOS inside it, and an N-well should be more positive than the P+ source/drain diffusions of the PMOS inside. If you have only one option of P-well (because the substrate is P-type), then you have only one option of \$V_{SS}\$; likewise, if you have only one option of N-well (because the substrate is N-type), then you have only one option of \$V_{DD}\$.

Most electronics are pretty happy to have only one \$V_{SS}\$, because more often than not it's the system ground. \$V_{DD}\$, on the other hand, is quite commonly a collection of voltages (for example, 2.5V, 3.3V, 5V...), and therefore it's useful for a circuit to have multiple N-wells so that it can interface with these different power domains. For this reason, P-sub/N-well processes are more popular than N-sub/P-well for CMOS.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.