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I am laying out a data bus at the moment (initially on breadboard), and I am wondering if there is a 'right' way to lay it out. I have a CPU acting as the bus master, and a number of devices (RAM, ROM, IO, etc) linked on to the bus.

We're talking no more than a few MHz of processor clock here - nothing incredibly fast.

Is it better to have the bus master device at one end of the bus (like this):

enter image description here

or is it OK to have the bus master in between other devices (like this)?

enter image description here

At the speeds we are talking, does it actually make any difference? I can foresee possible issues at much higher clock rates, but at say 4MHz is it a design consideration I should be thinking about?

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    \$\begingroup\$ The fact that you are on a bread board probably is a bigger issue than how the bus is connected. \$\endgroup\$ – Kellenjb Jul 12 '11 at 14:22
  • \$\begingroup\$ Yes, but when I move from breadboard to copper clad, should I be considering the placement of my components in relation to laying out the bus in a specific way? \$\endgroup\$ – Majenko Jul 12 '11 at 14:26
  • \$\begingroup\$ I guess the point I was trying to make was that if it works on a bread board then surely it will work on a PCB. \$\endgroup\$ – Kellenjb Jul 12 '11 at 14:38
  • \$\begingroup\$ At 4MHz you could get away with almost anything, bread-board, wire wrap, and practically whatever PCB layout you could think of, provided you don't actually go out of your way to create excessively long runs. If you're just hanging logic devices together within a foot or two of one another, there just won't be enough reactance to bother about. \$\endgroup\$ – JustJeff Jul 13 '11 at 1:48
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The location of the bus master doesn't matter. The important point is whether the bus is a transmission line or not, and therefore what steps need to be taken to ensure signal integrity. As Stevenvh pointed out, at 4MHz these are just digital signals on your board, and you probably need to do nothing special.

If the speed and or bus length went up such that it becomes a transmission line (lumped model no longer holds), then you have to deal with it as such. There are various things to do, depending on how far into transmission line territory you are. Common first steps are making sure the bus is only a single line with short drops (no star, for example) and terminating the ends. Sometimes just adding low value resistors to each bus driver is good enough. Diodes to clip overshoot and undershoot can help. However, if all this is done right it still doesn't matter whether the master (presumably the bus driver?) is in the middle or one of the ends.

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Kellenjb has a point about breadboarding this, but flatcables with interleaving grounds may help here.
The rule-of-thumb says that you start getting transmission line effects if the trace/wire length is greater than 1/10th of the wavelength. A 4MHz sine has a wavelength of 75m, but you'll need a few harmonics to get decent edges. 20 MHz means 15m wavelength, so expect transmission line effects from \$\pm\$ 1.5m. This will be much longer than your wiring so I don't expect problems, wherever you place the master.
If your bus uses pull-up/down resistors it's a good idea to place them at the end.

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  • \$\begingroup\$ +1 for pointing out the harmonics. gotta keep those edges reasonably square. \$\endgroup\$ – JustJeff Jul 13 '11 at 1:50
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At 4Mhz you have cycle time of 250ns.

Let's say you can ignore any delays without even thinking about them if they are not more than 1/4 of this.

To get 62ns delay you need 930cm-long trace (15cm per 1ns).

So, as long all your parts are within same building, you should be fine in any case.

There are other considerations: You may want to have proper termination & matching impedance of all devices on the bus to avoid reflections, which on this clock would not kill you, but it's better to live without it.

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  • \$\begingroup\$ Is this 1/4 rule an arbitrary thing, or what is it based upon? You're talking about delay, but transmission lines are much more than that; then we talk about reflections, characteristic impedance and group delay. \$\endgroup\$ – stevenvh Jul 12 '11 at 17:28
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    \$\begingroup\$ @stevenvh: The 1/4 rule probably stems from a couple of factors: (1) If edges are sampled on the clock edge opposite of when they change (preferred scenario when data transmitter supplies clock), a 1/4-cycle skew still leaves a full 1/4 cycle sample/hold time at the receiver. A 0.49-cycle skew would only leave 0.01 cycles for sample/hold; (2) any reflected signal will have bounced off both ends of the line by the end of a half-cycle, so if either end does a good job of absorbing reflections, the signal should be clean by that point. \$\endgroup\$ – supercat Jul 12 '11 at 21:05
  • \$\begingroup\$ @supercat Perfectly \$\endgroup\$ – BarsMonster Jul 12 '11 at 21:49
  • \$\begingroup\$ @BarsMonster: I forgot to mention that with SPI, one may have to reduce the time significantly below 1/4 of the propagation. If an SPI master expects to latch received data on the clock edge opposite the one where the slave transmitter will send it, then within 1/2 cycle of the master generating each active clock edge, the signal must reach the slave, the slave must generate the response, and the response must reach the master. If propagation time was e.g. 0.24 cycles, that would only leave 0.02 cycles for both the slave's response and the master's setup time requirements. \$\endgroup\$ – supercat Jul 12 '11 at 21:54

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